Abstract: It is an object of the present invention to provide a current-voltage conversion circuit in which the sensitivity varies in accordance with the amplitude of the input signal. In the current-voltage conversion circuit of the present invention, n+1 (n is an even number) amplifying inverters are connected in series between an input terminal and an output terminal; furthermore, the input of a negative feedback circuit constructed from an integrating circuit and a negative feedback inverter is connected to the output side of the nth-stage amplifying inverter, and the output of this negative feedback circuit is connected to the input side of the first-stage amplifying inverter. The integrating circuit outputs the mean value of the output potential of the nth-stage amplifying inverter into the negative feedback inverter, and the negative feedback inverter controls the current that flows the ground line from the input terminal in accordance with the output voltage of the integrating circuit.

Abstract: It is an object of the present invention to provide a current-voltage conversion circuit in which the sensitivity varies in accordance with the amplitude of the input signal. In the current-voltage conversion circuit of the present invention, n+1 (n is an even number) amplifying inverters are connected in series between an input terminal and an output terminal; furthermore, the input of a negative feedback circuit constructed from an integrating circuit and a negative feedback inverter is connected to the output side of the nth-stage amplifying inverter, and the output of this negative feedback circuit is connected to the input side of the first-stage amplifying inverter. The integrating circuit outputs the mean value of the output potential of the nth-stage amplifying inverter into the negative feedback inverter, and the negative feedback inverter controls the current that flows the ground line from the input terminal in accordance with the output voltage of the integrating circuit.

Abstract: A sequence controller includes a sequencer to which a basic clock is applied. The sequencer sequentially generates at a period of 125 &mgr;sec address signals for reading statements to be executed at a period of 125 &mgr;sec and one block of statements to be executed at a period of 10 msec or one block of statements to be executed at a period of 100 msec. A memory stores the above statements beforehand. The statements are selectively read out of the memory in accordance with the address signals and fed to a decoder. The decoder decodes the statements and generates control signals respectively corresponding to the statements and feeds the control signals to a switch. The switch controls each of a plurality of function registers on the basis of the respective control signal.

Abstract: A frame aligner detects sync patterns consisting of at least two units of data having a first value followed by at least two units of data having a second value in a serial data signal. The serial signal is demultiplexed to units of parallel data, which are stored in a shift register having a capacity of two units of data. All but one bit off the stored data are scanned to detect a unit having the first value. When such a unit is detected, alignment data indicating its position in the shift register are generated. The alignment data are latched and used to extract subsequent units from the shift register. New and old alignment data are compared to detect aligned units having the first value. A sync pattern is recognized as a consecutive sequence of such aligned units followed by a consecutive sequence of units having the second value.