Abstract: In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including a number of memory cells each having a floating gate and a control gate, an interlayer insulator film is formed to cover the control gate of the memory cells in the memory zone and a gate electrode formed in the peripheral circuit zone. A contact hole is formed through the interlayer insulator film to reach the gate electrode formed in the peripheral circuit zone, and is filled with a first conducting material. A groove is formed in the interlayer insulator film to longitudinally extend along a word line which constitutes the control gate of a plurality of memory cells arranged in one line. This groove penetrates through the interlayer insulator film to reach the word line over the whole length of the word line.

Abstract: A method for lapping a material to be lapped is provided, in which the material contacts with a surface of a rotating lapping cloth. A lapping agent containing lapping particles is employed. The lapping particles have a hardness identical or equivalent to that of the material. The hardness is adjusted by controlling a concentration of the lapping particles. A method for manufacturing the lapping particles for use in the lapping method is also provided, in which a silane and an oxygen are injected in a gaseous phase to generate porous silica particles having a desired concentration.

Abstract: A method for lapping a material to be lapped is provided, in which the material contacts with a surface of a rotating lapping cloth. A lapping agent containing lapping particles is employed. The lapping particles have a hardness identical or equivalent to that of the material. The hardness is adjusted by controlling a density of the lapping particles. A method for manufacturing the lapping particles for use in the lapping method is also provided, in which a silane and an oxygen are injected in a gaseous phase to generate porous silica particles having a desired density.

Abstract: In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including a number of memory cells each having a floating gate and a control gate, an interlayer insulator film is formed to cover the control gate of the memory cells in the memory zone and a gate electrode formed in the peripheral circuit zone. A contact hole is formed through the interlayer insulator film to reach the gate electrode formed in the peripheral circuit zone, and is filled with a first conducting material. A groove is formed in the interlayer insulator film to longitudinally extend along a word line which constitutes the control gate of a plurality of memory cells arranged in one line. This groove penetrates through the interlayer insulator film to reach the word line over the whole length of the word line.

Abstract: A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier method is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.

Abstract: The present invention provides a base layer structure formed in a hole having an upper portion which has a larger diameter than other portions thereof. The hole is formed in an insulation layer in a semiconductor device. The base layer structure comprises a base layer which extends on at least a part of the upper portion of the hole and over at least a part of the insulation layer in the vicinity of a top of the hole, wherein the base layer extending on the upper portion has an effective thickness in an elevational direction, which is thicker than a thickness of the base layer over the insulation film and also thicker than a critical thickness which allows that at least a part of the base layer on the upper portion of the hole remains after an anisotropic etching process, whilst the base layer having extended over the insulation layer is etched by the anisotropic etching process.

Abstract: A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier metal is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.

Abstract: A method of manufacturing a semiconductor device includes forming a base region and a collector region on an Si substrate, forming, on the base region, an emitter region of a semiconductor material having an energy gap larger than that of Si, forming an Si film on the emitter region, ion-implanting an element into a surface portion of the emitter region or at the interface of the emitter region and the Si film and a periphery portion of the interface, and simultaneously forming electrodes on the base and collector regions and on the Si film. A heterojunction bipolar transistor manufactured by the above method is also disclosed.