Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.

Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.

Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.

Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.

Abstract: A phase difference-detecting apparatus for detecting a relative distance between a pair of focused images obtained from subject luminous flux passed through an objective lens to thereby judge a focusing state of the objective lens. The apparatus includes a pair of signal generating sections which receive the subject flux and provide first and second time series signals. A switching-capacitor integrator is provided including a plurality of capacitive elements and switching elements for intermittently connecting the capacitive elements to each other, and for receiving the first and second time series signals. A control device compares the sizes of the first and second time series signals with each other to thereby generate a control signal corresponding to a relation of size between the first and second time series signals.

Abstract: In a comparator circuit comprising a first power supply terminal means and a second power supply terminal means, a differential stage connected between the first power supply terminal means and the second power supply terminal means, a first input signal having a reference level and a second input signal having a level which is compared with the reference level being input to each of a pair of input terminals of the differential stage, respectively, an output signal having a level which is determined in accordance with the level of the second input signal being output from an output terminal of the differential stage, and an output stage connected to the output terminal of the differential stage, through which output stage the output signal of the differential stage is amplified; a bypass circuit through which a predetermined constant current flows is connected between the output terminal of the differential stage and the second power supply terminal means.

Abstract: A semiconductor integrated circuit including; an inverter circuit including a pair of transistors of different conductivities and a level shift circuit, one transistor being supplied with an input signal via the level shift circuit, the other transistor being supplied with the input signal directly, and the level shift circuit having an amount of level shift such that, when an input signal of a transition level for distinguishing a logic level in the inverter circuit is received, the level of the input signal via the level shift circuit is shifted near to the threshold level of the other transistor.

Abstract: The semiconductor integrated circuit includes a first power supply terminal and a second power supply terminal; a first transistor and a second transistor having gates (or bases) connected in common; an input terminal and an output terminal connected to each source (or each emitter) of the first and second transistors, respectively, an output voltage level being obtained from the output terminal in accordance with an input signal voltage level supplied to the input terminal; and a current mirror circuit operating so that a first current flows through the first transistor in proportion to a second current flowing through the second transistor, the value of the second current is determined in accordance with the output voltage level and a value of a load connected between the output terminal and the second power supply terminal; and thereby, a voltage level supplied to the gates (or bases) of the first and second transistors is varied in accordance with the value of the second current.