Abstract: Provided is a display device including a pixel array forming by arranging a plurality of pixels whose display grayscale are controlled according to a pixel signal written, a signal line drive unit that outputs a pixel signal, to a plurality of signal lines, with a polarity according to a polarity signal, a scan line drive unit that drives the plurality of signal lines and performs a writing of the pixel signal output to the signal line into the pixels, a polarity signal generation unit that generates the polarity signal instructing the polarity of the pixel signal to be reversed, and supplies the result to the signal line drive unit, and a frame cycle set unit that generates the vertical start pulse in such a manner that a period of the number of vertical clocks that is not a multiple of the N is one frame period.

Abstract: A liquid crystal display device having pillar-shaped spacers formed in pixel array regions is provided with improved display quality by preventing the degradation of contrast and the occurrence of residual images. A plurality of pillar-shape spacers formed in their pixel array regions are provided at locations which do not overlap with each other when images are projected on the screen using three different liquid crystal light valves to project the red (R), green (G) and blue (B), constituents of images.

Abstract: The quality of an image is improved even if the duration of data voltage is short for application. A gate line driver 34 sequentially applies the gate voltage to a number of gate lines G1-Gm by predetermined duration. Data lines are grouped into four groups each consisting of n lines (d1A-dnA: group A, d1B-dnB: group B, d1C-dnC: group C, and d1D-dnD: group D). A data line driver 40 and a multiplexer 38 sequentially perform for the data line groups A-D in the above predetermined duration application of data voltage to each data line in a predetermined data line group. A precharge controller 44 and a voltage switching circuit 46 apply to each of the data line groups A-D, through a transistor 42, a precharge voltage (+V.sub.1 or -V.sub.1) with the same polarity with that of data voltage being applied next time during the time from previous application of the data voltage to next application of it.