Patents by Inventor Kunitaka Mori

Kunitaka Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5214677
    Abstract: In a sync detection circuit, an input pulse signal at frequency f.sub.0 is compared with an output pulse signal from a frequency divider to produce a control signal representative of a difference in frequency or phase between the input and output pulse signals. A voltage-controlled oscillator generates pulses at a frequency f.sub.0 .times.N (where N.gtoreq.2) when the control signal indicates that the frequency or phase difference is zero or pulses at a variable frequency when the control signal indicates that the frequency or phase difference is non-zero. The frequency divider divides the frequency of the pulses from the oscillator by a factor N to generate the output pulse signal. A decision circuit is provided for detecting when the pulses generated by the oscillator during an interval between pulses of the input pulse signal are equal to at least N to give an indication that a phase alignment is established between the input and output pulse signals.
    Type: Grant
    Filed: October 31, 1989
    Date of Patent: May 25, 1993
    Assignee: NEC Corporation
    Inventor: Kunitaka Mori
  • Patent number: 5089821
    Abstract: A digital data reproducing circuit suitable for use with a magnetic-recording apparatus comprises first and second comparators, a clock-generating circuit, first and second shift registers, and a discriminator. The first comparator determines when a positive amplitude of a reproduced analog signal exceeds a positive first level. The second comparator determines when a negative amplitude of the reproduced analog signal exceeds a negative first level. The clock generating circuit generates a clock signal phased-locked to timings of positive and negative peaks of the reproduced analog signal. The first shift register receives an output of the first or second comparator in response to the clock signal and shifts and stores such output. The second shift register receives an OR signal of outputs of the first and second comparators in response to the clock signal and shifts and stores such OR signal. The discriminator produces digital data from parallel outputs of the first and second shift registers.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: February 18, 1992
    Assignee: NEC Corporation
    Inventor: Kunitaka Mori
  • Patent number: 4890275
    Abstract: A reading circuit with improved accuracy for an optical disk apparatus, which includes two separate systems for processing the read-out signal from the photo-transducer. In the first system, the read-out signal is differentiated and then a zero-level detector generates a binary signal to indicate whether the differentiated signal is positive or negative, whereby the binary signal indicates whether the edges of the read-out signal are rising or falling. The second system is a pit detecting circuit which generates a pit detecting signal by comparing the read-out signal with a fixed reference voltage, the pit detecting signal thus indicating the spacing between pits in the read-out signal. An AND gate combines the pit detecting signal with the inverse of the binary signal, generating pulses in close synchronism with the rising edges of the pits on the optical disk, and these pulses are shaped so as to correspond very closely to the recorded information.
    Type: Grant
    Filed: April 8, 1988
    Date of Patent: December 26, 1989
    Assignee: NEC Corporation
    Inventor: Kunitaka Mori
  • Patent number: 4764916
    Abstract: A reading circuit with improved accuracy for an optical disk apparatus, which includes two separate systems for processing the read-out signal from the photo-transducer. In the first system, the read-out signal is differentiated and then a zero-level detector generates a binary signal to indicate whether the differentiated signal is positive or negative, whereby the binary signal indicates whether the edges of the read-out signal are rising or falling. The second system is a pit detecting circuit which generates a pit detecting signal by comparing the read-out signal with a fixed reference voltage, the pit detecting signal thus indicating the spacing between pits in the read-out signal. An AND gate combines the pit detecting signal with the inverse of the binary signal, generating pulses in close synchronism with the rising edges of the pits on the optical disk, and these pulses are shaped so as to correspond very closely to the recorded information.
    Type: Grant
    Filed: March 5, 1986
    Date of Patent: August 16, 1988
    Assignee: NEC Corporation
    Inventor: Kunitaka Mori