Abstract: To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

Abstract: To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

Abstract: An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

Abstract: A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit processor. If the received instruction is analyzed to be a 32-bit processor instruction, the control unit controls the 32-bit processor with the aid of two 16-bit instruction control units. If the received instruction is a 16-bit processor instruction, the 32-bit processor control unit sends a 16-bit processor mode signal to each of the 16-bit instruction control units. One of the two 16-bit instruction control units controls one of two 16-bit processors which are divisions of the 32-bit processor while the other 16-bit instruction control unit controls the other 16-bit processor. The present invention makes it possible to have a single, wide bitwidth processor serve as a plurality of narrow bitwidth processors depending upon the type of processing.

Abstract: A program controlled processor comprises a scalar processing unit 101 for normal data (=scalar) operations and branch processing, a plurality of vector processing units 102 of identical structure, a vector distributor 103 for distributing input data as block vectors to vector memory 304 in each vector processing unit 102, a vector coupler 104 for coupling the block vectors stored in vector memory 404 in each vector processing unit 102 to provide output vectors, an instruction memory 105 for storing the operations of these circuit blocks as an operating program, a sequencer 106 for sequentially reading the instruction memory 105, and a decoder 107 for interpreting the read instructions and outputting a control signal to each circuit block. The scalar processing unit 101 comprises a scalar bus input enabling the scalar processing unit 101 to refer scalar registers in the vector processing units 102.

Abstract: The digital processor includes an instruction memory, a sequencer, a decoder, and a memory reference control circuit. In case the sequencer reads the external memory reference instruction, the memory reference control circuit serves to fetch an external memory reference instruction signal and an operand of the external memory reference signal delivered from the decoder, hold the operand until the external memory cycle executed by the external memory reference instruction is terminated, and release the operand when the cycle is terminated. The sequencer serves to have succeeding instructions read out continuously while the external memory reference instruction is being executed, and to concurrently execute the read-out instructions when the read-out instructions refer to resources not occupied by the external memory reference instruction, so as to execute the read-out instructions in parallel with the external memory reference instruction, thereby improving the throughput of the total processing.

Abstract: In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction.

Abstract: A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder.

Abstract: A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

Abstract: A sum-of-products calculating circuit includes a bit extension circuit, wherein the most significant bit of an intermediate result of the multiplication effected by a multiplier is extended from an order one bit of the order higher than that of the most significant bit of the intermediate result of the multiplication to the sign bit of addition input data to an adder, by using the most significant bit of each of two intermediate results of the multiplication effected by a multiplier and the sign bit of each of multiplication input data to the multiplier. The data having the extended data bits are inputted to an adder as addition data for the addition performed therein. Thereby, the number of bits used for representing output data of the multiplier can be equalized with that of bits used for representing input data of the adder by a simple logic circuit without the addition of dummy bits to the addition data. Thus, the component elements of the calculating circuit is substantially reduced in number.

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.1 column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract: To extend the function of a bipolar type RAM, a register function is added to the RAM function. The register function is such that the contents stored in a memory cell is inputted to a differential switch, and the output to the differential switch is derived out to constantly read out the stored content of a desired bit with a simple circuit construction.

Abstract: This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.