Patents by Inventor Kuniyasu Shimizu

Kuniyasu Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5884021
    Abstract: The present invention provides a computer system with an interruption resistance which construction costs are greatly reduced by eliminating lock-run-out sequence when restarting is performed. In a computer system with an interruption resistance, comprising a check point restart function, special process for taking check points are respectively provided for processors included in the computer system. When taking a check point, the special process for taking check points is brought into an ready state by a wake-up portion. After the special process for taking check points takes a check point, the special process for taking check points is brought into a sleep state again. In this manner, check points are not taken when executing an arbitrary process, and therefore, lock-run-out can be eliminated when restarting is performed.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: March 16, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Hirayama, Kuniyasu Shimizu
  • Patent number: 5845326
    Abstract: A computer system including a plurality of processors and a copyback cache memory and a method for periodically obtaining a first and second phase memory checkpoints and recovering from faults using the checkpoints, are disclosed. The computer system has cache flush hardware for executing a cache flush operation independently of the processors, including cache flush starters for starting the cache flush hardware, and cache flush end detectors for detecting the end of the cache flush operation. During a first phase checkpoint, the cache flush and normal data processing are done in parallel. When the cache flush end detectors detect the termination of the cache flush hardware, the processors suspend normal data processing, and a second checkpoint step is executed in which the processors save the context of the processors in the main memory and the cache flush hardware is invoked again so that dirty data in the cache memory is written back in to the main memory.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: December 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Hirayama, Kuniyasu Shimizu
  • Patent number: 5752268
    Abstract: A recoverable disk control system for a computer system that includes a checkpoint operation. When an operating system generates a write request to a disk device, the write request and the associated write data are stored into a nonvolatile memory. The operating system is immediately notified as if the write request were completed. The writing the data to the disk device is postponed until the next checkpoint. At the end of the next checkpoint execution, the write request is scheduled for execution. In that case a fault occurs before the write request is scheduled, the write request is discarded.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: May 12, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kuniyasu Shimizu, Hideaki Hirayama