Patents by Inventor Kuniyuki Kakushima

Kuniyuki Kakushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942490
    Abstract: A photon counting radiation detector includes a cell structure including a substrate and an epitaxial layer provided on the substrate, radiation being incident on the epitaxial layer; an inclination ? of the substrate being set in a predetermined range, where tsub is a thickness of the substrate, tepi is a thickness of the epitaxial layer, L is a length of the substrate, and the inclination ? is an inclination of the substrate with respect to an incident direction of the radiation. The epitaxial layer is preferably one type selected from SiC, Ga2O3, GaAs, GaN, diamond, and CdTe. Such a photon counting radiation detector is preferably a direct converting type.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 26, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki Kakushima, Akito Sasaki, Atsuya Sasaki, Hideaki Hirabayashi
  • Patent number: 11652150
    Abstract: Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 16, 2023
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kuniyuki Kakushima, Takuya Hoshii, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Taiki Yamamoto
  • Publication number: 20230012093
    Abstract: The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer.
    Type: Application
    Filed: December 4, 2020
    Publication date: January 12, 2023
    Applicant: Tokyo Institute of Technology
    Inventors: Kuniyuki KAKUSHIMA, Hiroshi FUNAKUBO, Shun-ichiro OHMI, Joel MOLINA REYES, Ichiro FUJIWARA, Atsushi HORI, Takao SHIMIZU, Yoshiko NAKAMURA, Takanori MIMURA
  • Patent number: 11513149
    Abstract: One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 29, 2022
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kuniyuki Kakushima, Takuya Hoshii, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Taiki Yamamoto
  • Publication number: 20210175268
    Abstract: A photon counting radiation detector includes a cell structure including a substrate and an epitaxial layer provided on the substrate, radiation being incident on the epitaxial layer; an inclination ? of the substrate being set in a predetermined range, where tsub is a thickness of the substrate, tepi is a thickness of the epitaxial layer, L is a length of the substrate, and the inclination ? is an inclination of the substrate with respect to an incident direction of the radiation. The epitaxial layer is preferably one type selected from SiC, Ga2O3, GaAs, GaN, diamond, and CdTe. Such a photon counting radiation detector is preferably a direct converting type.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki KAKUSHIMA, Akito SASAKI, Atsuya SASAKI, Hideaki HIRABAYASHI
  • Patent number: 10964836
    Abstract: According to one embodiment, a photon counting-type radiation detector includes a first cell and a second cell. The first cell transmits radiation. The second cell is stacked with the first cell. The second cell absorbs the radiation passing through the first cell.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD
    Inventors: Kuniyuki Kakushima, Tomoyuki Suzuki, Kazuo Tsutsui, Akito Sasaki, Atsuya Sasaki, Hideaki Hirabayashi, Yoshinori Kataoka
  • Publication number: 20200225276
    Abstract: One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.
    Type: Application
    Filed: August 6, 2018
    Publication date: July 16, 2020
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kuniyuki KAKUSHIMA, Takuya HOSHII, Hitoshi WAKABAYASHI, Kazuo TSUTSUI, Hiroshi IWAI, Taiki YAMAMOTO
  • Publication number: 20200203493
    Abstract: Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.
    Type: Application
    Filed: August 6, 2018
    Publication date: June 25, 2020
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kuniyuki KAKUSHIMA, Takuya HOSHII, Hitoshi WAKABAYASHI, Kazuo TSUTSUI, Hiroshi IWAI, Taiki YAMAMOTO
  • Publication number: 20200041663
    Abstract: According to one embodiment, a photon counting-type radiation detector includes a first cell and a second cell. The first cell transmits radiation. The second cell is stacked with the first cell. The second cell absorbs the radiation passing through the first cell.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD
    Inventors: Kuniyuki KAKUSHIMA, Tomoyuki SUZUKI, Kazuo TSUTSUI, Akito SASAKI, Atsuya SASAKI, Hideaki HIRABAYASHI, Yoshinori KATAOKA
  • Patent number: 10283776
    Abstract: The present invention provides an electrode material comprising at least one of metal compound powder and carbon powder, the powder having an average particle size of 50 ?m or less and an activation energy E? of 0.05 eV or less. Further, the powder preferably has hopping conduction characteristics at room temperature of 25° C. Furthermore, the powder preferably has an amount of oxygen defects of 1×1018 cm?3 or more. Still further, the powder preferably has a carrier density of 1×1018 cm?3 or more. Due to above structure, there can be provided an electrode material having a high storage capacity and a high charge/discharge efficiency.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 7, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Akito Sasaki, Hideyuki Oozu, Yoshinori Kataoka, Kuniyuki Kakushima, Wei Li, Hiroshi Iwai
  • Publication number: 20170256797
    Abstract: The present invention provides an electrode material comprising at least one of metal compound powder and carbon powder, the powder having an average particle size of 50 ?m or less and an activation energy E? of 0.05 eV or less. Further, the powder preferably has hopping conduction characteristics at room temperature of 25° C. Furthermore, the powder preferably has an amount of oxygen defects of 1×1018 cm?3 or more. Still further, the powder preferably has a carrier density of 1×1018 cm?3 or more. Due to above structure, there can be provided an electrode material having a high storage capacity and a high charge/discharge efficiency.
    Type: Application
    Filed: August 27, 2015
    Publication date: September 7, 2017
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Akito SASAKI, Hideyuki OOZU, Yoshinori KATAOKA, Kuniyuki KAKUSHIMA, Wei LI, Hiroshi IWAI
  • Patent number: 9343536
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 17, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Kazuo Tsutsui, Hiroshi Iwai, Kuniyuki Kakushima, Hitoshi Wakabayashi
  • Publication number: 20160043187
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.
    Type: Application
    Filed: February 13, 2015
    Publication date: February 11, 2016
    Inventors: Wataru Saito, Kazuo Tsutsui, Hiroshi Iwai, Kuniyuki Kakushima, Hitoshi Wakabayashi
  • Patent number: 9214626
    Abstract: A resistance change memory device with a high ON/OFF radio can be provided according to an embodiment includes a first electrode containing a first element, a resistance change layer provided on the first electrode and containing an oxide of the first element, an oxygen conductive layer provided on the resistance change layer, containing a second element and oxygen, having oxygen ion conductivity, and having a relative permittivity higher than a relative permittivity of the resistance change layer, and a second electrode provided on the oxygen conductive layer. The resistance change layer undergoes dielectric breakdown earlier than the oxygen conductive layer when a voltage between the first electrode and the second electrode is continuously increased from zero.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 15, 2015
    Assignees: TOKYO INSTITUTE OF TECHNOLOGY, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki Kakushima, Chunmeng Dou, Parhat Ahmet, Hiroshi Iwai, Yoshinori Kataoka
  • Publication number: 20150083987
    Abstract: A resistance change memory device with a high ON/OFF ratio can be provided. A resistance change memory device according to an embodiment includes a first electrode containing a first element, a resistance change layer provided on the first electrode and containing an oxide of the first element, an oxygen conductive layer provided on the resistance change layer, containing a second element and oxygen, having oxygen ion conductivity, and having a relative permittivity higher than a relative permittivity of the resistance change layer, and a second electrode provided on the oxygen conductive layer. The resistance change layer undergoes dielectric breakdown earlier than the oxygen conductive layer when a voltage between the first electrode and the second electrode is continuously increased from zero.
    Type: Application
    Filed: March 12, 2013
    Publication date: March 26, 2015
    Applicants: TOKYO INSTITUTE OF TECHNOLOGY, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki Kakushima, Chunmeng Dou, Parhat Ahmet, Hiroshi Iwai, Yoshinori Kataoka
  • Patent number: 7825755
    Abstract: A semiconductor substrate; a cantilever which is formed on the semiconductor substrate so as to face the semiconductor substrate with an air layer therebetween, the cantilever being made from an electrically conductive material or a semiconductor material, and the cantilever being mechanically movable; a photodiode which is formed so as to be connected in parallel to a capacitance that is constituted from the cantilever and the semiconductor substrate, and the photodiode being formed between an anchor portion which is a portion of the cantilever and the semiconductor substrate; and a power source which supplies voltage via a resistance on a side of the cantilever which is a connection point of a parallel circuit including both the capacitance and the photodiode so as to be backward bias to the photodiode, are included.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: November 2, 2010
    Assignee: The Foundation for the Promotion of Industrial Science
    Inventors: Hiroshi Toshiyoshi, Hiroyuki Fujita, Yuko Yamauchi, Akio Higo, Kuniyuki Kakushima
  • Patent number: 7800181
    Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
  • Publication number: 20090102006
    Abstract: A semiconductor substrate; a cantilever which is formed on the semiconductor substrate so as to face the semiconductor substrate with an air layer therebetween, the cantilever being made from an electrically conductive material or a semiconductor material, and the cantilever being mechanically movable; a photodiode which is formed so as to be connected in parallel to a capacitance that is constituted from the cantilever and the semiconductor substrate, and the photodiode being formed between an anchor portion which is a portion of the cantilever and the semiconductor substrate; and a power source which supplies voltage via a resistance on a side of the cantilever which is a connection point of a parallel circuit including both the capacitance and the photodiode so as to be backward bias to the photodiode, are included.
    Type: Application
    Filed: April 7, 2005
    Publication date: April 23, 2009
    Inventors: Hiroshi Toshiyoshi, Hiroyuki Fujita, Yuko Yamauchi, Akio Higo, Kuniyuki Kakushima
  • Publication number: 20090057739
    Abstract: The Ge channel device comprises: a Ge channel layer (2); a Si-containing interface layer (4) formed on the Ge channel layer (2); a La2O3 layer (6) formed on the interface layer (4); and an electrically conductive layer (8) formed on the La2O3 layer (6). In this device, the Si-containing interface layer (4) functions to suppress the diffusion of Ge atoms into the La2O3 layer (6) and thereby prevents the formation of Ge oxide in the La2O3 layer (6); accordingly, a Ge channel device whose C-V characteristic exhibits only a small hysteresis can be achieved.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: Tokyo Institute of Technology
    Inventors: Hiroshi Iwai, Takeo Hattori, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, Jaeyeol Song, Masaki Yoshimaru, Yasuyoshi Mishima, Tomonori Aoyama, Hiroshi Oji, Yoshitake Kato
  • Publication number: 20070093047
    Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 26, 2007
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima