Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A socket includes multiple protrusions and grooves alternatively formed in the inner periphery of the central hole of the socket. Each protrusion has an encounter face formed on the distal end thereof. The encounter face includes two inclined faces which intersect at a peak point by a top angle. Each protrusion includes two lateral sides which respectively face the grooves corresponding thereto. The two inclined faces respectively intersect the two lateral sides at a corner by a corner angle which is an obtuse angle. An angle of 2 to 9 degrees is defined between each of the inclined face and a chord that passes the peak point and is perpendicular to an axis of the protrusion. The center angle between the two lateral sides of each protrusion is 25 to 44 degrees and the engagement between the two inclined faces and the worn object can be enhanced.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.

Abstract: A waterproof electrical connector includes a connector body and a waterproof cap. The connector body includes a mating island surrounded by a ring groove. The mating island defines a mating face and plural passageways. The passageways receive conductive terminals and penetrate through the mating face. A soft cushion is set inside the waterproof cap. The connector body includes a collar portion. The collar portion is higher than the mating face and forms an entrance cavity around the ring groove. When the cap covers the connector body, the soft cushion penetrates into the entrance cavity to press and seal the mating face.

Abstract: A photonic semiconductor device including a light-emitting component and a photonic integrated circuit is provided. The light-emitting component at least includes a gain medium layer, a first contact layer and a first optical coupling layer stacked to each other. The photonic integrated circuit includes a second optical coupling layer. The light-emitting component and the photonic integrated circuit are stacked in a stacking direction, the first optical coupling layer has a first taper portion, the second optical coupling layer has a second taper portion, and the first taper portion and the second taper portion overlap in the stacking direction. Accordingly, the light emitted from the gain medium layer may be transmitted to the second taper portion from the first taper portion by optical coupling in a short length of an optical coupling path.

Abstract: A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.

Abstract: Optical devices and methods of manufacture are presented in which an opening is formed within a first semiconductor device and then bonded to other optical devices. A laser die or other fill material may be used to refill the opening. The first semiconductor device is then electrically connected to an optical interposer.

Abstract: A method includes forming an optical engine, which includes a photonic die. The photonic die further includes a grating coupler. The method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. The optical fiber extends into the groove. The fiber platform further includes a reflector. The fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.

Abstract: A method includes patterning a top silicon layer in a substrate to form a plurality of photonic devices. The substrate includes the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer. The method further includes forming a second dielectric layer to embed the plurality of photonic devices therein, forming an interconnect structure over and signally coupling to the plurality of photonic devices, bonding an electronic die to the interconnect structure, thinning the semiconductor layer, and patterning the semiconductor layer that has been thinned to form openings. The openings are filled with a dielectric material to form dielectric regions. Through-vias are formed to penetrate through the dielectric regions to electrically couple to the interconnect structure.

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulant, and forming an interconnect structure over and electrically connecting to the first device die and the second device die. A waveguide is formed in the interconnect structure. An optical-engine based interconnect component is bonded to the interconnect structure. The optical-engine based interconnect component forms a part of a signal path that connects the first device die to the second device die.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Abstract: An LED backlight driver includes at least one driving chip configured to drive a backlight module. The at least one driving chip is disposed on at least one chip-on-film package, and not in direct contact with the backlight module to reduce heat transfer to the backlight module.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A chip includes an instruction storage unit, a processor core, an input circuit, a neural network circuit, power-consuming circuits, and a switch circuit. When the chip runs, the processor core performs a processing operation according to the instructions under being supplied with a current. At the same time, the neural network circuit predicts an upcoming change of the current according to data stream, representing the time-varying current, from the input circuit, and outputs a corresponding control signal. The switch circuit selectively provides a clock to one or more power-consuming circuits under the control of the control signal, so that each power-consuming circuit receiving the clock operates under being supplied with the current. Therefore, the chip can predict upcoming requirement of high electricity consumption, and duly start up a current wasting mechanism in advance, to avoid an excessive voltage drop without affecting operation efficiency of the processor core.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

Abstract: Predictive multi-stage modelling for complex semiconductor device manufacturing process control is provided. In one aspect, a method of predictive multi-stage modelling for controlling a complex semiconductor device manufacturing process includes: collecting geometrical data from metrology measurements made at select stages of the manufacturing process; and making an outcome probability prediction at each of the select stages using a multiplicative kernel Gaussian process, wherein the outcome probability prediction is a function of a current stage and all prior stages. Machine-learning models can be trained for each of the select stages of the manufacturing process using the multiplicative kernel Gaussian process. The machine-learning models can be used to provide probabilistic predictions for a final outcome in real-time for production wafers. The probabilistic predictions can then be used to select production wafers for rework, sort, scrap or disposition.

Abstract: An approach for utilizing an IC (integrated circuit) that is capable of storing multi-bit in storage is disclosed. The approach leverages the use of multiple nanowires structures as channels in a gate of a transistor. The use of multiple nanowires as channels allows for different Vt (i.e., voltage of device) to be dependent on the thickness of the fe (ferroelectric layer) that surrounds each of the nanowire channels. Memory window is about 2d (thickness of a fe layer). Setting voltage is also proportional to the fe layer thickness. The Vt of the device is the superposition of the various fe layers. For example, if there are three channels with three different Fe layer (of varying thickness), then four memory states can be achieved. More states can be achieved based on the number of channels in the device.