Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.

Abstract: The address conversion system includes a storage device, a memory bus, and a processor. The processor is configured to execute the following steps: generating a real buffer on the storage device; generating a fake buffer in a fake capacity of the storage device by a fake buffer algorithm; establishing a coupling relationship between the real buffer and the fake buffer through a coupling algorithm by the coupler of the memory bus; receiving a compressed data from a first device by the real buffer; when a second device wants to read the fake buffer, the coupler guides the second device to the real buffer through the coupling relationship for reading; transmitting the compressed data of the real buffer to the coupler by the memory bus; decompressing the compressed data into a decompressed data by the coupler; and transmitting the decompressed data to the second device by the memory bus.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: The present invention provides a thermosetting method to form a porous polytetrafluoroethylene membrane, wherein a heat flow in a heat circulating environment is provided to ensure the porous polytetrafluoroethylene membrane is heated uniformly. A thermal heating radiation plat is further used that being heated by the heat flow to generate a far-infrared radiation for providing an enhanced heating effect without extra energy consuming sources. The thermosetting method of porous polytetrafluoroethylene membrane not only maintain a uniformity temperature inside the heating compartment, stabilize the quality of the polytetrafluoroethylene porous membrane, but also make the thermosetting process more efficiently without using extra energy input.

Abstract: An antenna structure includes a metal frame, at least one feed source, and a feed portion. The metal frame includes at least one radiating portion and at least one slot. The at least one slot is disposed in the at least one radiating portion or adjacent to the at least one radiating portion. The at least one feed source and the at least one radiating portion form a first antenna. The feed portion and the at least one slot form a second antenna. The at least one feed source supplies an electric current for the first antenna, thereby exciting a first working mode and generating a radiation signal in a first frequency band. The feed portion spans the at least one slot to supply the electric current for the second antenna, thereby exciting a second working mode and generating a radiation signal in a second frequency band.

Abstract: An antenna structure applied in a wireless communication device includes a metal frame. The wireless communication device includes at least one electronic component. The metal frame includes a substrate. The substrate includes an antenna. The antenna includes a feed portion and a gap. The feed portion spans the gap. The metal frame is spaced from the electronic component. A clearance is formed between the metal frame and the electronic component.

Abstract: An antenna and antenna module with a structure increasing radio wave coverage but reducing cross interference between modules includes a circuit board in the shape of an octagon and four antenna modules. The circuit board thus includes eight side surfaces, and the four antenna modules are respectively disposed on four non-adjacent side surfaces of the octagon. Each antenna module is electrically connected to the side surface by a feed portion. A wireless communication device using the antenna structure is also disclosed.

Abstract: An antenna structure includes a metal frame. The metal frame includes a first surface, a second surface, and a third surface. The third surface is located between the first surface and the second surface. The metal frame includes at least one antenna. The at least one antenna includes a first gap, a second gap, and a feed portion. The first gap is disposed between the first surface and the second surface. The second gap is disposed in the third surface. The feed portion is mounted on the first surface and spans the first gap. When the feed portion supplies an electric current, the electric current is coupled to the first gap and the second gap.

Abstract: An antenna structure capable of transmitting radio waves in multiple polarizations is positioned on a circuit board. The circuit board includes upper and lower surfaces and peripheral side wall. The antenna structure includes a first antenna array, a second antenna array, and a control circuit. Each antenna unit of the first antenna array is positioned on one of the upper surface or the lower surface, a portion of each antenna unit of the second array is positioned on the peripheral side wall. The other portion of each antenna unit bended and positioned on at least one of the upper surface or the lower surface. In activating the first antenna array and the second antenna array the control circuit can generate radio transmissions in multiple polarizations. A wireless communication device is also provided.