Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

Abstract: A semiconductor structure includes a semiconductor fin, a doped dielectric fin, a shallow trench isolation (STI) oxide, a gate structure, and source/drain regions. The semiconductor fin upwardly extends from a substrate. The doped dielectric fin upwardly extends above the substrate. The doped dielectric fin is implanted with an impurity therein. The STI oxide laterally surrounds a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin. The gate structure extends across the semiconductor fin and the doped dielectric fin. The source/drain regions are on the semiconductor fin and at opposite sides of the gate structure.

Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.

Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer.

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

Abstract: The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.

Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: A semiconductor device includes a substrate and a semiconductor structure over the substrate. The semiconductor device also includes a first dielectric structure over the substrate, and the first dielectric structure has a first height. The semiconductor device further includes a second dielectric structure over the substrate, and the second dielectric structure has a second height. The second height is smaller than the first height. In addition, the semiconductor device includes a first gate stack wrapped around the first dielectric structure, and the semiconductor structure and the second dielectric structure are spaced apart from the first gate stack. The semiconductor device includes a second gate stack wrapped around the second dielectric structure and the semiconductor structure, and the second gate stack is electrically isolated from the first gate stack.