Patents by Inventor Kuo Cheng Yu

Kuo Cheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363687
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chung-Wei HSU, Chih-Hao WANG, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Mao-Lin HUANG
  • Publication number: 20240363732
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Jia-Ni YU, Chun-Fu LU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240355625
    Abstract: A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 ? to about 20 ?.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12119391
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240339456
    Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang
  • Patent number: 12107131
    Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240322013
    Abstract: A method for manufacturing a semiconductor structure includes forming first and second channel layers over a substrate, forming first source/drain features over the first and second channel layers, forming a gate dielectric layer wrapping around the first and second channel layers, forming a first work function layer wrapping around the gate dielectric layer, forming a hard mask layer wrapping around the first work function layer, removing portions of the hard mask layer and the first work function layer, removing the hard mask layer and the first work function layer wrapping around the second channel layer, removing the hard mask layer wrapping around the first channel layer, forming a second work function layer wrapping around the first work function layer and the second channel layer, forming a metal material between the second work function layer, and forming second source/drain features under the first and second channel layers.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fu LU, Chih-Hao Wang, Wang-Chun Huang, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
  • Publication number: 20240322041
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 26, 2024
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Publication number: 20240312993
    Abstract: An integrated circuit includes an NMOS gate all around (GAA) transistor and a PMOS GAA transistor. A single gate metal is utilized for both transistors. An effective work function is imparted to the NMOS transistor by including a first layer of the gate metal around the channels, a semiconductor layer around the first layer of the gate metal, and a gate fill layer of the gate metal on the semiconductor layer. The PMOS transistor, the gate fill layer of the gate metal is on the gate dielectric without an intervening semiconductor layer.
    Type: Application
    Filed: July 18, 2023
    Publication date: September 19, 2024
    Inventors: Chung-Wei HSU, Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240312845
    Abstract: A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12094948
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Patent number: 12087771
    Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12087772
    Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240282587
    Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 22, 2024
    Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240274604
    Abstract: A semiconductor device structure is provided. The structure includes a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material. The structure also includes a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material, wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.
    Type: Application
    Filed: April 3, 2024
    Publication date: August 15, 2024
    Inventors: Mao-Lin HUANG, Jia-Ni YU, LUNG-KUN CHU, Chung-Wei HSU, Chih-Hao WANG, Kuo-Cheng CHIANG, Kuan-Lun CHENG
  • Patent number: 12062693
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 12057486
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen
  • Publication number: 20240243186
    Abstract: A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 18, 2024
    Inventors: Chun-Fu LU, Lung-Kun CHU, Jia-Ni YU, Mao-Lin HUANG, Chung-Wei HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240243178
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 18, 2024
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12040191
    Abstract: A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 ? to about 20 ?.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang