Abstract: A cell activation reactor and a cell activation method are provided. The cell activation reactor includes a body, a rotating part, an upper cover, a microporous film, and multiple baffles. The body has an accommodating space, which is suitable for accommodating multiple cells and multiple magnetic beads. The rotating part is disposed in the accommodating space and includes multiple impellers. The microporous film is disposed in the accommodating space and covers multiple holes of the accommodating space. The baffles are disposed in the body. When the rotating part is driven to rotate, the interaction between the baffles and the impellers separates the cells and the magnetic beads.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.

Abstract: A method for performing network control in a wireless communications system and associated apparatus are provided. The method may include: carrying a set of link information in a preamble of a first data transmission frame transmitted from the first network device to a second network device, wherein the set of link information may include at least one indication among the following indications: a destination device indication, a device assignment indication and a transmission power control indication; wherein a third network device is arranged to monitor wireless transmission in the wireless communications system to obtain the set of link information from the first data transmission frame, and determine spatial reuse (SR) transmission availability of the third network device based on the set of link information.

Abstract: An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.

Abstract: A dental mirror structure contains a body and a connector. The body includes an inspector, a connection segment, and a first air conduit. The inspector includes a lens, and the first air conduit has an inlet and an outlet adjacent to the lens. The connector is hollow and columnar, and the connector includes a second air conduit defined on a center thereof, a connection portion extending from a first end of the connector, a first stem extending from the connection portion, a second stem extending from a second end of the connector, and a fixing extension extending from the second end of the connector and surrounding the second stem. Thereby, the first stem is connected with an air supply element, the second stem is fitted with the inlet the body, and the fixing extension is connected with the connection segment.

Abstract: A semiconductor arrangement is provided and includes a gate electrode. The gate electrode includes a first portion over a first interface between an active region and an isolation structure and a second portion over the active region. The first portion has a first material composition. The second portion has a second material composition different than the first material composition.

Abstract: An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively.

Abstract: A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Abstract: A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.

Abstract: A multi-level DC-DC converter device includes an inverter, a 3-winding high-frequency transformer, a first full-bridge rectifier, a second full-bridge rectifier, a selective circuit and a filter circuit. A first winding at a primary side of the high-frequency transformer connects with the inverter while a second winding and a third winding of at a secondary side of the high-frequency transformer connect with the first full-bridge rectifier and the second full-bridge rectifier. The selective circuit connects with DC output ports of the first full-bridge rectifier and the second full-bridge rectifier, thereby operationally selecting two serially-connected full-bridge rectifiers or single full-bridge rectifier to output two voltage levels performed as a multi-level output voltage. The filter circuit connects between the selective circuit and a load for filtering harmonics and outputting a DC voltage.

Abstract: A DC-DC converter is operated in a boost mode by operating a plurality of low-voltage side switches with a first fixed duty cycle (greater than 0.5), with cutting off a plurality of the first high-voltage side switches and a plurality of the second high-voltage side switches, with conducting a plurality of the first diodes of the first high-voltage side switches and a plurality of the second diodes of the second high-voltage side switches, and with alternatively conducting and cutting off a bidirectional switch. In a buck mode, the low-voltage side switches are cut off and a plurality of diodes of the low-voltage side switches are conducted. Furthermore, the first high-voltage side switches are complemented and are operated with a second fixed duty cycle (less than 0.5) while the second high-voltage side switches are conducted and cut off alternatively and the bidirectional switch is switched on and off.

Abstract: A DC-DC converter is operated in a boost mode by operating a plurality of low-voltage side switches with a first fixed duty cycle (greater than 0.5), with cutting off a plurality of the first high-voltage side switches and a plurality of the second high-voltage side switches, with conducting a plurality of the first diodes of the first high-voltage side switches and a plurality of the second diodes of the second high-voltage side switches, and with alternatively conducting and cutting off a bidirectional switch. In a buck mode, the low-voltage side switches are cut off and a plurality of diodes of the low-voltage side switches are conducted. Furthermore, the first high-voltage side switches are complemented and are operated with a second fixed duty cycle (less than 0.5) while the second high-voltage side switches are conducted and cut off alternatively and the bidirectional switch is switched on and off.