Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.

Abstract: In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Method for providing obstacle avoidance using depth information of image is provided. The method includes the following steps. Shoot a scene to obtain a depth image of the scene. Determine a flight direction and a flight distance according to the depth image. Then, fly according to the flight direction and the flight distance.

Abstract: An electrical actuator with hammering mechanism includes a driving device, a transmission assembly driven by the driving device, an arc slot formed in the transmission assembly, a hammer element arranged in the arc slot, and a power valve arranged at one side of the hammer element. The driving device, when in operation, drives the transmission assembly to rotate and the arc slot is set in rotation in unison with the transmission assembly, while the hammer element is held at one side of the power valve so that a relative movement is generated between the arc slot and the hammer element. Thus, at the beginning of rotation of the transmission assembly, before the arc slot gets into impact with the hammer element, no loading that results in resistance is present so that full speed rotation can be conducted to thereby increase the kinetic energy before activation of the power valve.

Abstract: A speed adjustable returning apparatus for an electric actuator utilizes a cooperative configuration between the one-way driving device and the clutch device during the use of the apparatus in order to prevent damages caused by the operating unit driven by the opening/closing assembly. In addition, the clutch device is able to allow the operating device to selectively drive the opening/closing assembly in order to prevent impacts on the opening/closing assembly due to accidental movements of the operating device. Consequently, the present invention is able to achieve the effect of preventing damages of relevant equipment and providing a safer uses for applications.

Abstract: Method for providing obstacle avoidance using depth information of image is provided. The method includes the following steps. Shoot a scene to obtain a depth image of the scene. Determine a flight direction and a flight distance according to the depth image. Then, fly according to the flight direction and the flight distance.

Abstract: A speed-adjustable returning device of a valve actuator including a transmission assembly, an energy storage device arranged at one side of the transmission assembly and is operatively coupled thereto, an arrestment device arranged beside the energy storage device and is operatively coupled to the transmission assembly, and a valve device arranged at one side of the transmission assembly and is operatively coupled thereto. Under a condition of normal power supply, the energy storage device is controlled to store energy, and when power supply is interrupted, the energy storage device releases the stored energy to drive the transmission assembly to operate in a reversed direction so that the transmission assembly drives the arrestment device in such a way that the arrestment device makes the transmission assembly and the energy storage device operated at fixed speeds to thereby make the valve device operated at a fixed speed.

Abstract: A linear travel structure of an electrical operating device includes a body, a substrate, a cover, a first transmission assembly, a second transmission assembly, and a third transmission assembly. The body receives the substrate to mount thereto so as to enclose and define a first receiving space. The cover is mounted to the body and, together with the substrate, encloses and defines a second receiving space. The substrate includes an electrical machine mounted thereto and received in the second receiving space. The first transmission assembly, the second transmission assembly, and the third transmission assembly are all received in the first receiving space. The electrical machine is connected in cascade with the first, second, and third transmission assemblies for operation therewith. With such a multiple-staged transmission arrangement, advantages including high transmission efficiency, high bearing capacity, high speed ratio, and small volume, can be achieved over the conventional devices.

Abstract: An improved device, for actuating a valve, comprises a housing and a gear train accommodated in the housing. The gear train includes a center gearset, a planet-pinion carrier, and an output internal gear. The center gearset includes a first external gear and a second external gear being coaxially fixed to the first external gear. The planet-pinion carrier is mounted around the first external gear of the center gearset, wherein a first bearing is provided between the center gearset and the planet-pinion carrier; at least three pinions are mounted at a bottom or inside of the planet-pinion carrier, the pinions being meshed with the first external gear of the center gearset. The output internal gear is mounted in mesh with the pinions, wherein a second bearing is provided between the output internal gear and the housing. The present invention is durable in structure and has a high transmission efficiency.

Abstract: A linear travel structure of an electrical operating device includes a body, a substrate, a cover, a first transmission assembly, a second transmission assembly, and a third transmission assembly. The body receives the substrate to mount thereto so as to enclose and define a first receiving space. The cover is mounted to the body and, together with the substrate, encloses and defines a second receiving space. The substrate includes an electrical machine mounted thereto and received in the second receiving space. The first transmission assembly, the second transmission assembly, and the third transmission assembly are all received in the first receiving space. The electrical machine is connected in cascade with the first, second, and third transmission assemblies for operation therewith. With such a multiple-staged transmission arrangement, advantages including high transmission efficiency, high bearing capacity, high speed ratio, and small volume, can be achieved over the conventional devices.

Abstract: An improved device, for actuating a valve, comprises a housing and a gear train accommodated in the housing. The gear train includes a center gearset, a planet-pinion carrier, and an output internal gear. The center gearset includes a first external gear and a second external gear being coaxially fixed to the first external gear. The planet-pinion carrier is mounted around the first external gear of the center gearset, wherein a first bearing is provided between the center gearset and the planet-pinion carrier; at least three pinions are mounted at a bottom or inside of the planet-pinion carrier, the pinions being meshed with the first external gear of the center gearset. The output internal gear is mounted in mesh with the pinions, wherein a second bearing is provided between the output internal gear and the housing. The present invention is durable in structure and has a high transmission efficiency.

Abstract: A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module with reference to a synchronization signal.

Abstract: An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.

Abstract: A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes.

Abstract: An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.

Abstract: A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module with reference to a synchronization signal.

Abstract: A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes.

Abstract: The present invention discloses a glitch-free frequency dividing circuit, comprising: a frequency dividing module, dividing the frequency of a reference pulse according to the divisor, outputting a frequency divided output pulse and receiving a control signal such that the state of the frequency divided output pulse is maintained the same when the control signal is enabled; and a latch module, detecting the state of the frequency divided output pulse after a divisor switching signal is received, enabling the control signal when the frequency divided output pulse is as pre-determined, switching the divisor when the frequency divided output pulse is as pre-determined and disabling the control signal after the divisor is switched; whereby the generation of the glitch is prevented during the switching of the divisor.