Patents by Inventor Kuo-Hsin Lai
Kuo-Hsin Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150095741Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.Type: ApplicationFiled: December 18, 2013Publication date: April 2, 2015Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Shao-Wei Yen, Yu-Hsiang Lin, Kuo-Hsin Lai, Kuo-Yi Cheng
-
Publication number: 20150067446Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.Type: ApplicationFiled: October 16, 2013Publication date: March 5, 2015Inventors: Shao-Wei Yen, Yu-Hsiang Lin, Wei Lin, Kuo-Hsin Lai, Kuo-Yi Cheng
-
Publication number: 20140293696Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.Type: ApplicationFiled: May 24, 2013Publication date: October 2, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai, Yu-Cheng Hsu, Kuo-Yi Cheng
-
Patent number: 8832526Abstract: A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information.Type: GrantFiled: July 26, 2011Date of Patent: September 9, 2014Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Patent number: 8830750Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.Type: GrantFiled: June 26, 2013Date of Patent: September 9, 2014Assignee: Phison Electronics Corp.Inventors: Kuo-Yi Cheng, Wei Lin, Yu-Hsiang Lin, Shao-Wei Yen, Kuo-Hsin Lai
-
Publication number: 20140047300Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.Type: ApplicationFiled: October 28, 2012Publication date: February 13, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Li-Chun Liang, Tien-Ching Wang, Kuo-Hsin Lai
-
Patent number: 8510637Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.Type: GrantFiled: May 16, 2011Date of Patent: August 13, 2013Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Patent number: 8429501Abstract: A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.Type: GrantFiled: November 16, 2010Date of Patent: April 23, 2013Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Patent number: 8386860Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.Type: GrantFiled: May 27, 2010Date of Patent: February 26, 2013Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai, Li-Chun Liang
-
Publication number: 20120311402Abstract: A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information.Type: ApplicationFiled: July 26, 2011Publication date: December 6, 2012Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Patent number: 8289771Abstract: A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information.Type: GrantFiled: August 23, 2010Date of Patent: October 16, 2012Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Publication number: 20120072805Abstract: A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.Type: ApplicationFiled: November 16, 2010Publication date: March 22, 2012Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Publication number: 20110317488Abstract: A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information.Type: ApplicationFiled: August 23, 2010Publication date: December 29, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Publication number: 20110258495Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.Type: ApplicationFiled: May 27, 2010Publication date: October 20, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai, Li-Chun Liang
-
Publication number: 20110258496Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.Type: ApplicationFiled: May 16, 2011Publication date: October 20, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
-
Publication number: 20100115153Abstract: An adaptive multi-channel controller and its method for a storage device are provided for data transmission between a host and the storage device. The storage device is configured to have multiple channels. A channel use amount is determined based on a data access amount of the host. Then, activated channels are selected among the channels according to the channel use amount. The data transmission is then carried out through the selected channels.Type: ApplicationFiled: February 19, 2009Publication date: May 6, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Feng-Hsiang Lo, Kuo-Hsin Lai, Fu-Chiang Jan, Chia-Hang Ho, Hsin-Jung Chen, Chin-Yuan Wang, Po-Chang Chen
-
Patent number: 7549103Abstract: A data encoding method for error correction is provided. Before recording data into a recording media, the data are added with an Error Correction Code (ECC) comprising Check Sum on Row (CSR) and Check Sum on Column (CSC), thereby forming an ECC block. More than one ECC block are integrated into a data matrix, to resist longer burst errors of data. Finally, the data matrix is divided into several sectors and individual sector address information is added for each sector, thereby finishing the encoding process.Type: GrantFiled: May 10, 2006Date of Patent: June 16, 2009Assignee: Industrial Technology Research InstituteInventors: Ming-Chang Tsai, Che-Kuo Hsu, Kuo-Hsin Lai
-
Publication number: 20070136636Abstract: A data encoding method for error correction is provided. Before recording data into a recording media, the data are added with an Error Correction Code (ECC) comprising Check Sum on Row (CSR) and Check Sum on Column (CSC), thereby forming an ECC block. More than one ECC block are integrated into a data matrix, to resist longer burst errors of data. Finally, the data matrix is divided into several sectors and individual sector address information is added for each sector, thereby finishing the encoding process.Type: ApplicationFiled: May 10, 2006Publication date: June 14, 2007Applicant: Industrial Technology Research InstituteInventors: Ming-Chang Tsai, Che-Kuo Hsu, Kuo-Hsin Lai