Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.

Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A light emitting device includes a rectifier circuit, a mutual inductance device coupled to the rectifier circuit, an energy-storing capacitor coupled to a comm on node of a primary winding and a secondary winding of the mutual inductance device, a light emitting unit coupled to the mutual inductance device, a switch unit coupled to the light emitting unit, and a control circuit. The control circuit is coupled to the energy-storing capacitor and controls operation of the switch unit according to a voltage across the energy-storing capacitor.

Abstract: A light emitting device includes a rectifier circuit, a mutual inductance device coupled to the rectifier circuit, an energy-storing capacitor coupled to a common node of a primary winding and a secondary winding of the mutual inductance device, a light emitting unit coupled to the mutual inductance device, a switch unit coupled to the light emitting unit, and a control circuit. The control circuit is coupled to the energy-storing capacitor and controls operation of the switch unit according to a voltage across the energy-storing capacitor.

Abstract: A combined nasal spray and aspirator device includes an air pump disposed within a housing and comprises a spray and aspirator assembly. The air pump, at which an air suction connector and an air discharge connector are disposed, is driven by a driving component to perform air suction and discharge actions. The spray and aspirator assembly, mounted to the air suction connector and the air discharge connector, comprises a spray conduit and a first aspiration conduit; the spray conduit connects to an atomizer which is provided with liquids from a liquid storage container, and the first aspiration conduit connects to a mucus collector so that when some air carrying mucus enters the mucus collector, the mucus is left behind and the air enters the air pump through a second aspiration conduit. The device of the present invention integrates the operations of a nasal spray and a nasal aspirator, sucking the mucus away right after it sprays and liquefies the mucus, with said actions occurring almost simultaneously.

Abstract: A combined nasal spray and aspirator device includes an air pump disposed within a housing and comprises a spray and aspirator assembly. The air pump, at which an air suction connector and an air discharge connector are disposed, is driven by a driving component to perform air suction and discharge actions. The spray and aspirator assembly, mounted to the air suction connector and the air discharge connector, comprises a spray conduit and a first aspiration conduit; the spray conduit connects to an atomizer which is provided with liquids from a liquid storage container, and the first aspiration conduit connects to a mucus collector so that when some air carrying mucus enters the mucus collector, the mucus is left behind and the air enters the air pump through a second aspiration conduit. The device of the present invention integrates the operations of a nasal spray and a nasal aspirator, sucking the mucus away right after it sprays and liquefies the mucus, with said actions occurring almost simultaneously.

Abstract: This invention provides a device with a test strip-ejecting mechanism, which includes a casing and a test strip-ejecting mechanism installed inside the casing. The casing is provided with an insert opening collimated with a connector inside the casing for receiving a test strip. The test strip-ejecting mechanism includes a body provided with a guide groove and having an ejection base formed on a front end of the body, a block disposed inside the casing to define the body to slide along a predetermined direction in conjunction with the guide groove, and a spring providing the body a restoring force along the predetermined direction. The ejection base is disposed at the predetermined direction for ejecting the test strip from the connector along the predetermined direction. The present invention also provides a method for ejecting the test-strip.

Abstract: A sphygmomanometer is disclosed. The sphygmomanometer mainly includes multiple power buttons and multiple memory buttons mounted thereon, and the power buttons and the memory buttons are disposed in a corresponding manner for communicating with one another. Through pressing one of the power buttons, a measurement value of blood pressure can be directly stored into a correspondingly memory area, and by pressing one of the memory buttons which is corresponding to that power button, the stored measurement value is recalled and displayed on the displaying screen. Therefore, the sphygmomanometer can be provided for more than two users and can also respectively memorize (store) individual measurement value of blood pressure for each user. Furthermore, a selecting switch for selectively inactivating any selected power button is provided so that secure storage of personal information is also ensured.

Abstract: A sphygmomanometer is disclosed. The sphygmomanometer mainly has plural power buttons and plural memory buttons mounted thereon, and said power buttons and said memory buttons are in a one-on-one manner to communicate with one another. Through pressing one of said power buttons, a measurement value of blood pressure can be directly stored into a correspondingly memory area, and through pressing one of said memory buttons corresponding to that power button, said stored measurement value can be recalled and displayed on said display screen. Therefore, the sphygmomanometer can be provided for more than two users and also can respectively memorize (store) individual measurement value of blood pressure for each user.

Abstract: A probe structure for an ear thermometer includes a housing, a sleeve component, a sensor unit and a holding component. The housing has a first containing room to contain the sleeve component having a second containing room. The sleeve component has a front end formed with a reflective surface. The sensor unit is placed inside the second containing room and has a window, via which the sensor unit detects heat radiation. The sleeve component is used to lower heat radiation impact upon the sensor unit and prevent inexact measurements by the sensor unit caused by detecting objects other than the measured object. The sleeve component helps to reflect heat radiation from the measured object to the infrared sensor. This sensor unit functions well even though it is not disposed at the front most end of the probe. The holding component has one end against the bottom of the sensor unit.

Abstract: A sphygmomanometer is disclosed. The sphygmomanometer mainly has plural power buttons and plural memory buttons mounted thereon, and said power buttons and said memory buttons are in a one-on-one manner to communicate with one another. Through pressing one of said power buttons, a measurement value of blood pressure can be directly stored into a correspondingly memory area, and through pressing one of said memory buttons corresponding to that power button, said stored measurement value can be recalled and displayed on said display screen. Therefore, the sphygmomanometer can be provided for more than two users and also can respectively memorize (store) individual measurement value of blood pressure for each user.

Abstract: A sphygmomanometer is disclosed. The sphygmomanometer mainly includes multiple power buttons and multiple memory buttons mounted thereon, and the power buttons and the memory buttons are disposed in a corresponding manner for communicating with one another. Through pressing one of the power buttons, a measurement value of blood pressure can be directly stored into a correspondingly memory area, and by pressing one of the memory buttons which is corresponding to that power button, the stored measurement value is recalled and displayed on the displaying screen. Therefore, the sphygmomanometer can be provided for more than two users and can also respectively memorize (store) individual measurement value of blood pressure for each user. Furthermore, a selecting switch for selectively inactivating any selected power button is provided so that secure storage of personal information is also ensured.