Patents by Inventor Kuo-Jung Wang

Kuo-Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Patent number: 11961769
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20240105644
    Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11915971
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 8579645
    Abstract: A connector mechanism for connecting a board card is disclosed. The connector mechanism includes a circuit board, and a connector installed on the circuit board. An end of the board card is for inserting into the connector. The connector mechanism further includes a socket installed on the circuit board and located on a side of the connector, a rotating component pivoted to the socket, and at least one connecting component slidably installed on the rotating component and coupled to the circuit board for contacting with the other end of the board card so as to electrically connect to the board card as the end of the board card is inserted into the connector and the rotating component rotates to a connection position.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 12, 2013
    Assignee: Wistron Corporation
    Inventors: Kuo-Jung Wang, Chih-Chin Yang, Yu-Ming Chiu, Chun-Lung Hsiao, Ming-Chen Chiu, Jen-Hao Liu
  • Publication number: 20120289066
    Abstract: A connector mechanism for connecting a board card is disclosed. The connector mechanism includes a circuit board, and a connector installed on the circuit board. An end of the board card is for inserting into the connector. The connector mechanism further includes a socket installed on the circuit board and located on a side of the connector, a rotating component pivoted to the socket, and at least one connecting component sliably installed on the rotating component and coupled to the circuit board for contacting with the other end of the board card so as to electrically connect to the board card as the end of the board card is inserted into the connector and the rotating component rotates to a connection position.
    Type: Application
    Filed: March 27, 2012
    Publication date: November 15, 2012
    Inventors: Kuo-Jung Wang, Chih-Chin Yang, Yu-Ming Chiu, Chun-Lung Hsiao, Ming-Chen Chiu, Jen-Hao Liu
  • Patent number: 8075644
    Abstract: A catalytic liquid fuel is described, including a liquid fuel added with at least one kind of catalytic ion or its salt to improve the oxidation activity thereof. The liquid fuel includes at least an organic liquid fuel or a reducing agent or their mixture. The oxidation activity of the fuel can be enhanced by adding an extremely low concentration of the catalytic ion or it salt. The catalytic liquid fuel also can overcome problems like low oxidation activity, surface poisoning and fading of catalysts.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: December 13, 2011
    Assignee: National Taiwan University of Science and Technology
    Inventors: Bing-Joe Hwang, Jing-Shan Do, Shao-Kang Hu, Ching-Hsiang Chen, Kuo-Jung Wang, Sakkarapalayam Murugesan Senthil Kumar, Loka Subramanyam Sarma
  • Publication number: 20110102406
    Abstract: A gate driver applied to a LCD apparatus is disclosed. The gate driver includes a pulse modulation controlling module. When a pulse modulation controlling signal received by the pulse modulation controlling module is changed from a high level to a low level, the pulse modulation controlling module closes an active switch according to the pulse modulation controlling signal, so that a high level power signal will begin discharging to have a modulated pulse form.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 5, 2011
    Inventors: Chien-Kuo Wang, Kuo-Jung Wang, Wei-Ming Chen, Chin-Chieh Chao
  • Publication number: 20100166194
    Abstract: In the specification and drawing an apparatus for processing audio is described and shown with an audio processor for acquiring at least one audio signal from an audio chip and transforming the audio signal into a surround sound signal and a transmitter for emitting the surround sound signal to a radio set. Moreover, a method for processing audio is also disclosed in the specification and drawing.
    Type: Application
    Filed: September 30, 2009
    Publication date: July 1, 2010
    Applicant: WISTRON CORP.
    Inventors: Wen-Chun TSAO, Fang-Yuan CHIU, Kuo-Jung WANG, Chun-Chieh CHEN, Kuo-Hsing WANG, Chia-Hsien LI
  • Publication number: 20080066376
    Abstract: A catalytic liquid fuel is described, including a liquid fuel added with at least one kind of catalytic ion or its salt to improve the oxidation activity thereof. The liquid fuel includes at least an organic liquid fuel or a reducing agent or their mixture. The oxidation activity of the fuel can be enhanced by adding an extremely low concentration of the catalytic ion or it salt. The catalytic liquid fuel also can overcome problems like low oxidation activity, surface poisoning and fading of catalysts.
    Type: Application
    Filed: June 8, 2007
    Publication date: March 20, 2008
    Applicant: National Taiwan University of Science and Technology
    Inventors: Bing-Joe Hwang, Jing-Shan Do, Shao-Kang Hu, Ching-Hsiang Chen, Kuo-Jung Wang, Sakkarapalayam Murugesan Senthil Kumar, Loka Subramanyam Sarma
  • Patent number: 6597589
    Abstract: A power converter, and more particularly a switched AC/DC converter, is provided with an input current shaping (ICS) function. The ICS function is carried out by adjusting the conducting angle of the input current for a rectifier coupled to a central tap of a main transformer, thereby obtaining a higher power factor. Owing to the action of the ICS, the ripples in the feedback signal are usually larger. The ripples are used to modulate the switching frequency to effectively disperse and planarize the electromagnetic energy distribution of the power supply, and to suppress the electromagnetic interference problems of the power supply.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: July 22, 2003
    Assignee: Delta Electronics, Inc.
    Inventor: Kuo-Jung Wang
  • Publication number: 20030112642
    Abstract: A power converter, and more particularly a switched AC/DC converter provided with input current shaping (ICS) function is disclosed. The ICS function is carried out by adjusting the conducting angle of the input current for the rectifier in virtue of the central tap of the main transformer, and a higher power factor can be obtained. Owing to the action of the ICS, the ripples on the feedback signal are usually larger. The present invention uses the ripples to modulate the switching frequency to effectively disperse and planarize the electromagnetic energy distribution of the power supply, and obviate the electromagnetic interference deficiency of the power supply.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventor: Kuo-Jung Wang