Patents by Inventor Kuo-Lih Chang

Kuo-Lih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230349753
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 2, 2023
    Applicant: Lutron Technology Company LLC
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Patent number: 11740123
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: August 29, 2023
    Assignee: Lutron Technology Company LLC
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Publication number: 20220155142
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Applicant: Lutron Technology Company LLC
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Patent number: 11243112
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 8, 2022
    Assignee: Lutron Technology Company LLC
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Publication number: 20200386613
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Application
    Filed: March 30, 2020
    Publication date: December 10, 2020
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Patent number: 10605652
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: March 31, 2020
    Assignee: Lutron Ketra, LLC
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Publication number: 20190170571
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 6, 2019
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Patent number: 10161786
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: December 25, 2018
    Assignee: Lutron Ketra, LLC
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Publication number: 20150377695
    Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Inventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
  • Publication number: 20100130101
    Abstract: Embodiments described herein provide a method for polishing a substrate surface. The methods generally include storing processing components in multiple storage units during processing, and combining the processing components to create a slurry while flowing the processing components to a polishing pad. A substrate is polished using the slurry, and the thickness of a material layer disposed on the substrate is determined. The flow rate of one or more processing components is then adjusted to affect the rate of removal of the material layer disposed on the substrate.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 27, 2010
    Inventors: YUCHUN WANG, Long Cheng, Kuo-Lih Chang, Wei-Yung Hsu, Wen-Chiang Tu
  • Publication number: 20100096360
    Abstract: Methods and apparatus are provided for polishing barrier layer materials. In one embodiment, a composition is provided for removing at least a barrier material from a substrate surface, including includes a base composition, a silica abrasive, a solvent, a pH between about 7 and about 10, and one or more components selected from the group of a metal passivating compound, an oxidizer, and an alumina abrasive. The composition may be used to chemical mechanical polishing process a substrate surface having a ruthenium-based barrier and one or more material selected from the group of a polysilicon layer, a dielectric layer, or metal layer.
    Type: Application
    Filed: October 15, 2009
    Publication date: April 22, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: You Wang, Yuchun Wang, Yan Wang, Kuo-Lih Chang, Jin Xu, Wen-Chaing Tu
  • Publication number: 20090061743
    Abstract: A method and apparatus for pre-conditioning a new soft polishing pad and processing a substrate on a soft polishing pad is described. The method includes coupling a soft polishing pad to a platen, contacting the processing surface of the soft polishing pad with a conditioning disk, applying a pressure conditioning disk, removing the conditioning disk from contact with the processing surface of the soft polishing pad, and contacting a first substrate with the processing surface of the soft polishing pad to perform a polishing process on the first substrate.
    Type: Application
    Filed: August 21, 2008
    Publication date: March 5, 2009
    Inventors: STEPHEN JEW, Jimin Zhang, Kuo-Lih Chang, Shih-Haur Shen, Wen-Chiang Tu
  • Publication number: 20080296619
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 4, 2008
    Applicant: Board of Trustees of the University of Illinois
    Inventors: Kuang Chien Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John H. Epple, Gregory Pickrell
  • Patent number: 7407863
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 5, 2008
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Kuang Chien Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John H. Epple, Gregory Pickrell
  • Publication number: 20050074927
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Inventors: Kuang Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John Epple, Gregory Pickrell