Patents by Inventor Kuo-Ming Tsai
Kuo-Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162051Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.Type: ApplicationFiled: April 27, 2023Publication date: May 16, 2024Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Patent number: 11972982Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.Type: GrantFiled: July 14, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung Tsai, Yu-Ming Lin, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Chandrashekhar Prakash Savant, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 11951569Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.Type: GrantFiled: May 12, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
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Publication number: 20240113221Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.Type: ApplicationFiled: November 28, 2023Publication date: April 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsiung TSAI, Shahaji B. MORE, Cheng-Yi PENG, Yu-Ming LIN, Kuo-Feng YU, Ziwei FANG
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Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
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Publication number: 20240084455Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.Type: ApplicationFiled: February 8, 2023Publication date: March 14, 2024Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Publication number: 20240079268Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
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Patent number: 10765932Abstract: A maze capable of changing rolling paths contains: a rotatable three-dimensional block formed in a six-sided cube shape and defined by twenty-six square cube units for matching with a central fixing element. The rotatable three-dimensional block includes nine of the twenty-six square cube units formed in a 3 by 3 grid arranged on the rotatable three-dimensional block, and each square cube unit has three sets of rotary layers so as to form twelve rotary layer units. The rotatable three-dimensional block includes at least one path having at least one visible window formed on the at least one path respectively. The at least one path is formed in any one of a T shape, a cross shape, and an arc shape on each square cube unit, and the at least one path includes a ball rolling therein and at least one channel which communicates with one another.Type: GrantFiled: October 2, 2019Date of Patent: September 8, 2020Inventors: Kuo-Ming Tsai, Peter Tsungyu Tsai
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Patent number: 10010787Abstract: A three-dimensional maze structure contains: at least one body and at least one ball. Each body includes a central shaft, multiple partitions, and multiple paths. Each path is defined between any two adjacent partitions, among each path and any two adjacent partitions is formed a trapezoidal oblique surface, and each partitions is distributed by multiple semi-trapezoidal stop pieces, the stop piece has two peripheral ribs horizontally extending outward from two sides of each path to prevent the ball rolling out respectively, and between two facing peripheral ribs of any two adjacent stop pieces is defined a window. Each path has multiple fences and plural passages arranged in an irregular manner. Each ball rolls in each path of each body and a point with the trapezoidal oblique surface, hence each ball rolls and is stopped by the stop piece and then moves through horizontal path of any two adjacent partitions.Type: GrantFiled: July 27, 2017Date of Patent: July 3, 2018Inventor: Kuo-Ming Tsai