Abstract: Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of ?1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.

Abstract: A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum.

Abstract: Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of ?1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.

Abstract: An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual.

Abstract: A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.

Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.

Abstract: A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum.

Abstract: A reference voltage circuit includes a first PMOS device having a first source, a first gate, and a first drain, wherein the first source is coupled to a power supply node; and a second PMOS device having a second source, a second gate and, a second drain. The second source is coupled to the power supply node. The first and the second PMOS devices have constant source-drain currents. The reference voltage circuit further includes a third PMOS device having a third source, a third gate, and a third drain; and a resistor coupled between the third drain and the ground. The third source is coupled to the power supply node. The first, the second, and the third gates are interconnected. The first, the second, and the third drains are virtually interconnected.

Abstract: An error corrector with a high use efficiency of a memory includes a memory, a bus device, an input buffer and an error correction module. The memory stores data. The bus device controls a memory access. The input buffer receives and temporarily stores a coded blockcode data, and writes the coded blockcode data in the memory through the bus device. The error correction module reads the coded blockcode data in the memory through the bus device and decodes it in rows and columns to thereby obtain decoded data and check bytes. The error correction module writes the decoded data in the memory through the bus device and discards the check bytes.

Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.

Abstract: A device and method for block code error correction. The device includes a block code input unit, an erasing address table, an error table and a decoder. The block code input unit is used to input a block code. The erasing address table and the error table have a plurality of erasing entities and error entities in rows and columns, respectively. The decoder decodes the block code in a row direction based on the erasing address table to find data errors on rows and update the error table, and updates the erasing address table in the row direction according to a first determination principle. Next, the decoder decodes the block code in a column direction based on the erasing address table to find data errors on columns and update the error table, and updates the erasing address table in the column direction according to a second determination principle.

Abstract: A device and method for block code error correction. The device includes a block code input unit, an erasing address table, an error table and a decoder. The block code input unit is used to input a block code. The erasing address table and the error table have a plurality of erasing entities and error entities in rows and columns, respectively. The decoder decodes the block code in a row direction based on the erasing address table to find data errors on rows and update the error table, and updates the erasing address table in the row direction according to a first determination principle. Next, the decoder decodes the block code in a column direction based on the erasing address table to find data errors on columns and update the error table, and updates the erasing address table in the column direction according to a second determination principle.

Abstract: A peanuts harvester includes a truck body, plant row dividers, stalk straighteners, peanut diggers, a plant feeder, a tilted conveyer, a horizontal conveyer, a peanut stripper and a peanut collector such that the dug peanut plants are conveyed to the horizontal conveyer where the upper stalks are held by the conveyer and the lower peanuts on roots are stripped by the peanut stripper, whereby the stripped peanuts are screened, cleaned and collected into bags for efficient integrated harvesting of peanuts.