Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifics the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.

Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifies the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.

Abstract: The present invention discloses a reset method for a digital circuit. The method includes: providing a clock signal to the digital circuit; keeping the clock signal at a logic level according to a first indicating signal; generating a reset signal for resetting the digital circuit; and recovering the clock signal to the digital circuit according to a second indicating signal.

Abstract: A method of processing a frame including a plurality of macro-blocks is provided. Each of the macro-blocks respectively includes M pixels. A local buffer is previously provided. The capacity of the local buffer is equal to the size of N pixels. M and N are both positive integers. N is smaller than or equal to M. A target area is first selected from the micro-blocks, and then N pixels within the target area are stored in the local buffer. Afterward, the method performs a deblock filtering procedure on the N pixels stored in the local buffer.

Abstract: The present invention discloses a reset method for a digital circuit. The method includes: providing a clock signal to the digital circuit; keeping the clock signal at a logic level according to a first indicating signal; generating a reset signal for resetting the digital circuit; and recovering the clock signal to the digital circuit according to a second indicating signal.

Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifies the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.

Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.

Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.