Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A network device includes a status displaying module, a network module, a processor, a power providing module, and a power saving circuit. The network module implements network functions of the network device. The status displaying module receives displaying signals from the network module. The processor directs the network module to implement the network functions. The power providing module provides power for the processor, the network module, and the status displaying module. The power saving circuit couples the displaying signals to obtain coupled signals and controls modes of the processor and the power providing module according to presence of the coupled signals.

Abstract: A network device includes a status displaying module, a network module, a processor, a power providing module, and a power saving circuit. The network module implements network functions of the network device. The status displaying module receives displaying signals from the network module. The processor directs the network module to implement the network functions. The power providing module provides power for the processor, the network module, and the status displaying module. The power saving circuit couples the displaying signals to obtain coupled signals and controls modes of the processor and the power providing module according to presence of the coupled signals.

Abstract: A transmission cable includes a cable (20) and a plug (10). The cable includes a communication line (22), a power line (26), a plurality of inner jackets, an outer jacket wrapping the communication line and the power line together, and a metallic jacket for wrapping the communication line. The power line includes a plurality of power conductors, and each of the power conductors is wrapped by one of the inner jackets. The communication line includes a plurality of communication conductors, and each of the communication conductors is wrapped by one of the inner jackets. The plug includes a shell (12), a socket (14) and a plurality of pins (16) disposed in the socket. Each of the communication conductors electrically connects with one of the pins respectively, one of the power conductors electrically connects with pins of the remaining pins, and the metallic jacket is electrically connected to the shell.

Abstract: An inrush current limiting circuit (12) includes a transistor (Q), a switch element (M), and a short-circuit protection circuit (121). An emitter of the transistor is as an input of the inrush current limiting circuit. An input of the switch element is connected to a collector of the transistor. A second output of the switch element is as an output of the inrush current limiting circuit. A first terminal of the short-circuit protection circuit is connected to a first output of the switch element. A second terminal of the short-circuit protection circuit is connected to a base of the transistor. A third terminal of the short-circuit protection circuit is connected to the second output of the switch element.

Abstract: A transmission cable includes a cable (20) and a plug (10). The cable includes a communication line (22), a power line (26), a plurality of inner jackets, an outer jacket wrapping the communication line and the power line together, and a metallic jacket for wrapping the communication line. The power line includes a plurality of power conductors, and each of the power conductors is wrapped by one of the inner jackets. The communication line includes a plurality of communication conductors, and each of the communication conductors is wrapped by one of the inner jackets. The plug includes a shell (12), a socket (14) and a plurality of pins (16) disposed in the socket. Each of the communication conductors electrically connects with one of the pins respectively, one of the power conductors electrically connects with pins of the remaining pins, and the metallic jacket is electrically connected to the shell.

Abstract: A power supply device (1) converting received power signals to direct current signals to ensure a load to work normally. The power supply device includes a transformer circuit (10), a rectifier circuit (11), and an inrush current control circuit (12). The transformer circuit converts the received power signals to alternating current signals. The rectifier circuit is connected to the transformer circuit, and converts the alternating current signals to direct current signals. The inrush current control circuit is connected to the rectifier circuit, for limiting inrush current from the power supply device. The inrush current control circuit includes a voltage divider resistor (R1) and a filter capacitor (C1). The filter capacitor is connected to the voltage divider resistor in series. In the invention, the power supply device uses the inrush current control circuit to limit the inrush current, thus life of the components is lengthened, and the power supply device is stable.