Patents by Inventor Kuo-Wei Lin
Kuo-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240155675Abstract: Techniques pertaining to adaptive transmission opportunity (TXOP) sharing for latency-sensitive traffic in wireless communications are described. An apparatus determines whether to activate an adaptive TXOP sharing mechanism with respect to a plurality of traffics having different latency requirements and pending transmission. In response to a positive determination, the apparatus utilizes the adaptive TXOP sharing mechanism in transmitting one or more traffics of the plurality of traffics associated with a plurality of stations (STAs) by performing either or both of: (i) selecting a candidate traffic from the one or more traffics of the plurality of traffics; and (ii) adjusting a transmission time of the candidate traffic in transmitting the candidate traffic during a TXOP.Type: ApplicationFiled: September 13, 2023Publication date: May 9, 2024Inventors: Kuo-Wei Chen, Ying-You Lin
-
Publication number: 20240144550Abstract: A computing device obtains an image depicting an image of a user's face. The computing device identifies facial features in the user's face in the image and extracts characteristics of the facial features in the user's face in the image. The computing device predicts a skin tone of the user's face depicted in the image and generates a face chart based on the facial feature characteristics. The computing device adjusts a color of a facial region in the face chart according to the predicted skin tone and obtains lighting characteristics of the image of the user's face. The computing device adjusts one or more colors in the face chart based on the lighting characteristics of the image of the user's face.Type: ApplicationFiled: September 22, 2023Publication date: May 2, 2024Inventors: Kuo-Sheng LIN, Guo-Wei LI
-
Publication number: 20240144719Abstract: A computing device obtains an image depicting an image of a user's face. The computing device identifies one or more regions in the image depicting skin of the user and generates a skin mask. A skin tone of the user's face is predicted and the skin mask is populated according to the predicted skin tone. The computing device defines feature points corresponding to facial features on the user's face and extracts pre-defined facial patterns matching facial features depicted in the image. The extracted pre-defined facial patterns are inserted into the skin mask based on the feature points and a hair mask identifying one or more regions depicting hair of the user is generated. The computing device extracts a hair region depicted in the image of the user based on the hair mask and inserts the hair region on top of the skin mask to generate a face chart.Type: ApplicationFiled: September 18, 2023Publication date: May 2, 2024Inventors: Guo-Wei LI, Kuo-Sheng LIN
-
Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
-
Publication number: 20240098960Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
-
Publication number: 20240088291Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
-
Publication number: 20240080890Abstract: Techniques pertaining to an efficient pre-channel reservation mechanism for target wake time (TWT) and restricted TWT (rTWT) in overlapping basic service set (OBSS) dense networks are described. A first station (STA) transmits a frame to reserve a reservation period. The first STA then communicates with a second STA during the reservation period which aligns at least partially with a target wake time (TWT) service period (SP) or a restricted TWT (rTWT) SP of the second STA.Type: ApplicationFiled: August 1, 2023Publication date: March 7, 2024Inventors: Ying-You Lin, Kuo-Wei Chen
-
Publication number: 20240077762Abstract: A display is disclosed. The display comprises a display panel, and an optical film disposed on a viewing side of the display panel. The optical film has a total haze ranging from 15% to 60%, an inner haze less than or equal to 10%, and a reflectivity satisfying the relationships of 0.35%?(RSCI-RSCE)?1.50% and RSCE?1.50%, wherein RSCI is an average reflectivity of diffuse component and specular component, and RSCE is an average reflectivity of diffuse component. By adjusting the total haze, inner haze and reflectivity of the optical film to satisfy the above relationship, the display can have good anti-glare properties, and the contrast ratio of the display will not be reduced too much to avoid the display quality be affected.Type: ApplicationFiled: April 10, 2023Publication date: March 7, 2024Applicant: BenQ Materials CorporationInventors: Yu-Wei Tu, Chih-Wei Lin, Kuo-Hsuan Yu
-
Publication number: 20240079051Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.Type: ApplicationFiled: November 8, 2022Publication date: March 7, 2024Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Tuo-Hung Hou, Fu-Cheng Tsai, Jian-Wei Su, Kuo-Hua Tseng
-
Publication number: 20240071981Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
-
Publication number: 20240072155Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
-
Publication number: 20230279718Abstract: An automatic vehicle-door activating sensing system and a method therefor are provided. The system includes: a distance sensing antenna module and an activating antenna module for generating signals; a processor generates a first distance information, a second distance information, and a activating information according to the signals. When the first distance information is less than a distance threshold and a waveform of the activating information changes, the processor generates and transmits a ready-to-activate signal to an in-vehicle system. When the second distance information is greater than the distance threshold, the processor generates and transmits a vehicle door activating signal to the in-vehicle system. The in-vehicle system can activate the vehicle door after receiving the signals in sequence. With one radar, the invention can automatically activate the vehicle door based on a user's position and kicking behavior, thereby preventing misoperation caused by detection.Type: ApplicationFiled: October 24, 2022Publication date: September 7, 2023Inventors: KUO WEI LIN, CHUN YEN CHEN
-
Patent number: 10082349Abstract: A heat conducting module includes a main body. The main body includes a first surface and a second surface. The first surface is thermally connected to a heat absorbing body. The second surface is opposite to the first surface and is fluidly connected to a channel. The second surface has a plurality of grooves disposed along a direction. The channel allows a fluid to flow a long the direction. Each of the grooves includes a first sub-groove and at least one second sub-groove. The first sub-groove at least has a third surface close to the first surface. The first sub-groove at least partially communicates with the second sub-groove, and the second sub-groove is at least partially fluidly connected with the third surface.Type: GrantFiled: January 6, 2016Date of Patent: September 25, 2018Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Chi-Chuan Wang, Kuo-Wei Lin
-
Publication number: 20170064866Abstract: A heat conducting module includes a main body. The main body includes a first surface and a second surface. The first surface is thermally connected to a heat absorbing body. The second surface is opposite to the first surface and is fluidly connected to a channel. The second surface has a plurality of grooves disposed along a direction. The channel allows a fluid to flow a long the direction. Each of the grooves includes a first sub-groove and at least one second sub-groove. The first sub-groove at least has a third surface close to the first surface. The first sub-groove at least partially communicates with the second sub-groove, and the second sub-groove is at least partially fluidly connected with the third surface.Type: ApplicationFiled: January 6, 2016Publication date: March 2, 2017Inventors: Chi-Chuan WANG, Kuo-Wei LIN
-
Publication number: 20150267966Abstract: A method of fabricating a heat exchanger unit is provided. The method includes forming a first heat exchange component by providing a first inlet interface device; providing a first outlet interface device; providing a first set of pipes; and connecting respective first ends of each of the first set of pipes to the first inlet interface device and connecting a respective second ends of the each of the first set of pipes to the first outlet interface device. The method further includes forming a second heat exchange component in the same fashion as the first heat exchange component. The method also includes overlapping the first and second heat exchange components and cross-coupling the first set of pipes and the second set of pipes at a plurality of joints.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicant: Metal Industries Research & Development CentreInventors: Kuo-Wei Lin, Hung-Lu Yen, Tai-Hsin Hsu, Yuan-Chih Lin, Da-Yu Lin, De-Chang Tsai
-
Patent number: 8942099Abstract: A method to realize IP flow mobility (IFOM) between 3GPP access and non-3GPP access over GTP based interfaces is proposed. A user equipment is connected to a PDN-GW via a 3GPP access network and a non-3GPP access network. The UE transmits an IFOM triggering message to the PDN-GW, which selects IP flows to be moved based on EPS bearer ID and IP flow description. The PDN-GW sends an Update Bearer Request to a WAG or ePDG, and updates its mapping table if the Update Bearer Request is successful. The UE also updates its mapping table upon receiving an IFOM acknowledgement from the WAG or ePDG. The PDN-GW initiates a 3GPP bearer modification procedure to move the selected IP flows.Type: GrantFiled: September 19, 2012Date of Patent: January 27, 2015Assignee: Mediatek Inc.Inventors: Shu-Hao Yeh, Kuo-Wei Lin, Po-Han Chiang, Wan-Jiun Liao, Chao-Chin Chou
-
Patent number: 7884471Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.Type: GrantFiled: December 14, 2005Date of Patent: February 8, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Ying Tsai, Shih-Ming Chen, Kuo-Wei Lin
-
Publication number: 20090111208Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.Type: ApplicationFiled: December 31, 2008Publication date: April 30, 2009Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yang-Tung FAN, Chiou-Shian Peng, Cheng-Yu Chu, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Lin
-
Patent number: 7485906Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.Type: GrantFiled: December 20, 2006Date of Patent: February 3, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yang-Tung Fan, Chiou-Shian Peng, Cheng-Yu Chu, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Lin
-
Publication number: 20080013605Abstract: A method of GPS bit synchronization is disclosed. The method includes the steps of a) receiving plural serial C/A Codes, wherein a data bit is formed by m C/A Codes; b) sequentially providing a bin number ranged from 0 to m?1 to the plural C/A Codes; c) setting a sampling value k; d) sequentially determining adjacent two C/A Codes, C/A Code nk and C/A Code (n+1)k, wherein n={0, 1, 2, 3, . . . }, and calculating a sign change aggregate value of each bin number ranged from 0 to m?1; e) repeating step d) till there are k bin numbers having the sign change aggregate value equal to or greater than a first threshold, and summing the k bin numbers for obtaining a lookup value; and f) acquiring a bit boundary of the data bit according to the lookup value in the plural serial C/A Codes.Type: ApplicationFiled: July 12, 2006Publication date: January 17, 2008Applicant: RoyalTek Company Ltd.Inventor: Kuo-Wei Lin