Patents by Inventor Kuo-Yao Cho
Kuo-Yao Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8658051Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.Type: GrantFiled: May 12, 2008Date of Patent: February 25, 2014Assignee: Nanya Technology Corp.Inventors: Kuo-Yao Cho, Wen-Bin Wu, Ya-Chih Wang, Chiang-Lin Shih, Chao-Wen Lay, Chih-Huang Wu
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Patent number: 7998660Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.Type: GrantFiled: October 16, 2008Date of Patent: August 16, 2011Assignee: Nanya Technology Corp.Inventors: Chiang-Lin Shih, Kuo-Yao Cho
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Patent number: 7915133Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.Type: GrantFiled: December 10, 2007Date of Patent: March 29, 2011Assignee: Nanya Technology Corp.Inventors: Kuo-Yao Cho, Wen-Bin Wu, Chiang-Lin Shih, Jen-Jui Huang
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Patent number: 7892712Abstract: An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result.Type: GrantFiled: May 22, 2008Date of Patent: February 22, 2011Assignee: Nanya Technology CorporationInventors: Chiang-Lin Shih, Feng-Yi Chen, Kuo-Yao Cho
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Patent number: 7799512Abstract: A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.Type: GrantFiled: April 30, 2007Date of Patent: September 21, 2010Assignee: Nanya Technology Corp.Inventors: Kuo-Yao Cho, Jen-Jui Huang
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Patent number: 7776496Abstract: A photomask layout pattern including an H-shaped pattern having a first opaque line pattern in parallel with a second opaque line pattern and a central zone connecting the first and second line patterns. A zebra-crossing-like dense line and space pattern is disposed in the central zone. The pitch of the zebra-crossing-like dense line and space pattern is beyond the resolution limit of an exposure tool such that light passing the central zone has an exposure energy that is not adequate to form corresponding line/space image on a photoresist.Type: GrantFiled: August 30, 2007Date of Patent: August 17, 2010Assignee: Nanya Technology Corp.Inventor: Kuo-Yao Cho
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Patent number: 7713882Abstract: A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, wherein photoresists are laid on the stack layer to form a plurality of photoresist elements. Thus, a plurality of pattern is formed on the target layer, and a portion of target layer's surface is exposed. Lastly, ion implanting is provided and defines a doped area as hard mask for the etching process.Type: GrantFiled: March 7, 2008Date of Patent: May 11, 2010Assignee: Nanya Technology CorporationInventors: Chien-Er Huang, Kuo-Yao Cho
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Publication number: 20100009294Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.Type: ApplicationFiled: October 16, 2008Publication date: January 14, 2010Inventors: Chiang-Lin Shih, Kuo-Yao Cho
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Publication number: 20090290134Abstract: A method for exposure is provided to avoid a rise in temperature of a lens set. First, a light beam passes through a first light-receiving region of the lens set to expose a pattern on a substrate, and the first light-receiving region has a rise in temperature. Thereafter, the first light-receiving region is moved away. Afterwards, the light beam passes through a second light-receiving region of the lens set so that the first light-receiving region has a drop in temperature.Type: ApplicationFiled: August 8, 2008Publication date: November 26, 2009Inventors: Chiang-Lin Shih, Kuo-Yao Cho
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Publication number: 20090233448Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.Type: ApplicationFiled: May 12, 2008Publication date: September 17, 2009Applicant: NANYA TECHNOLOGY CORP.Inventors: Kuo-Yao CHO, Wen-Bin WU, Ya-Chih WANG, Chiang-Lin SHIH, Chao-Wen LAY, Chih-Huang WU
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Publication number: 20090155733Abstract: A method of forming an iso space pattern is provided. In the method, a first material layer is provided, and then a second material layer and a patterned material layer are formed thereon. After that, a first patterned photoresist layer is formed on the patterned material layer to partially cover the patterned material layer and to partially expose the patterned material layer, and the second material layer is then partially removed by using the first patterned photoresist layer and the patterned material layer as a mask. Afterwards, the iso space pattern constituted by the etched second material layer is formed after the first patterned photoresist layer and the patterned material layer are removed. Due to twice photolithography and etching processes, it is likely to form the relatively narrow iso space pattern with use of existing photolithography equipments according to the method.Type: ApplicationFiled: March 18, 2008Publication date: June 18, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Kuo-Yao Cho, Feng-Yi Chen
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Publication number: 20090149024Abstract: A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, wherein photoresists are laid on the stack layer to form a plurality of photoresist elements. Thus, a plurality of pattern is formed on the target layer, and a portion of target layer's surface is exposed. Lastly, ion implanting is provided and defines a doped area as hard mask for the etching process.Type: ApplicationFiled: March 7, 2008Publication date: June 11, 2009Inventors: Chien-Er Huang, Kuo-Yao Cho
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Publication number: 20090111060Abstract: An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result.Type: ApplicationFiled: May 22, 2008Publication date: April 30, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Feng-Yi Chen, Kuo-Yao Cho
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Publication number: 20090029267Abstract: A photomask layout pattern including an H-shaped pattern having a first opaque line pattern in parallel with a second opaque line pattern and a central zone connecting the first and second line patterns. A zebra-crossing-like dense line and space pattern is disposed in the central zone. The pitch of the zebra-crossing-like dense line and space pattern is beyond the resolution limit of an exposure tool such that light passing the central zone has an exposure energy that is not adequate to form corresponding line/space image on a photoresist.Type: ApplicationFiled: August 30, 2007Publication date: January 29, 2009Inventor: Kuo-Yao Cho
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Publication number: 20080286934Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.Type: ApplicationFiled: December 10, 2007Publication date: November 20, 2008Applicant: NANYA TECHNOLOGY CORP.Inventors: Kuo-Yao CHO, Wen-Bin WU, Chiang-Lin SHIH, Jen-Jui HUANG
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Publication number: 20080251933Abstract: A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction.Type: ApplicationFiled: August 27, 2007Publication date: October 16, 2008Inventors: Kuo-Yao Cho, Wen-Bin Wu, Chiang-Lin Shih, Chia-Cheng Lin
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Publication number: 20080206684Abstract: A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.Type: ApplicationFiled: April 30, 2007Publication date: August 28, 2008Applicant: NANYA TECHNOLOGY CORP.Inventors: Kuo-Yao CHO, Jen-Jui HUANG