Abstract: A method of making a catalyst comprising mixing a metal oxide precursor and a pore former to form a metal oxide precursor mixture and calcining the metal oxide precursor mixture in the presence of a flowing gas having a flow rate to form the catalyst comprising metal oxide. The catalyst comprises a first distribution of pores having a median pore diameter of 10 to 50 angstroms and a second distribution of pores having a median pore diameter of 1 to 500 angstroms. The median pore diameter of the second distribution of pores is inversely related to the flow rate of the gas.

Abstract: A method of making a catalyst comprising mixing a metal oxide precursor and a pore former to form a metal oxide precursor mixture and calcining the metal oxide precursor mixture in the presence of a flowing gas having a flow rate to form the catalyst comprising metal oxide. The catalyst comprises a first distribution of pores having a median pore diameter of 10 to 50 angstroms and a second distribution of pores having a median pore diameter of 1 to 500 angstroms. The median pore diameter of the second distribution of pores is inversely related to the flow rate of the gas.

Abstract: Referring to FIGS. 20-24, in one embodiment, data can be transferred from the data register of a top adjacent timer channel (e.g. 400 in FIG. 20) to the data register of the timer channel itself (401), and from the data register of the timer channel itself (401) to the data register of the bottom adjacent timer channel (402). By programming control register bits (e.g. DVB bits 425-426, DTC bits 423-424, and DTS bits 427-428 in FIG. 21) of selected timer channels (401) to perform these inter-channel data transfers, both stacks and FIFO structures can be formed and used. Stack and FIFO data storage structures can reduce the frequency of service required by the timer channels (400-402), and thus reduce the number of interrupts which must be responded to by a CPU (13 in FIG. 1).

Abstract: A battery powered paging receiver for receiving paging messages includes a memory for storing address information for the paging receiver and for storing information related to features or functions of the paging receiver. When the address information of the received paging message corresponds to the stored address information, the paging receiver processes the received paging message in accordance with the stored information related to features or functions of the paging receiver.

Abstract: A data processor has a microcode memory which is reduced in size by sharing word locations having the same contents. When one of the shared word locations is addressed, a control signal is generated and coupled to a select circuit. The select circuit outputs a predetermined operand in place of the contents of the addressed shared word location which can contain a "do not care" operand value. Selective sharing or combining of the word locations is utilized when structuring the memory to optimize savings in circuit area.

Abstract: A battery powered receiver including a adaptive signal decoder is disclosed which is capable of processing detected encoded signals in accordance with a plurality of decoding schemes. The decoder has an equivalent microcomputer implementation. Energy conservation means operating independently of the detected signals acts to conserve the energy of the battery.

Abstract: An battery powered, adaptive signal decoder is disclosed which is capable of processing detected encoded signals in accordance with a plurality of decoding schemes. The decoder has an equivalent microcomputer implementation. Energy conservation means operating independently of the detected signals acts to conserve the energy of the battery.

Abstract: An erase circuit for an EEPROM is provided which only uses enhancement type transistors. This eliminates having to use additional processing steps to provide depletion type transistors in a CMOS process. Enhancement type transistors are used to provide the erase voltage to the control gate of an electrically erasable memory cell. An additional enhancement type transistor is used to maintain the control gate in a non-floating condition during non-erase periods.

Abstract: In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

Abstract: A data processor for performing a division operation requiring shifting and the counting of the number of shifts, having no dedicated counters therefor. An additional shift left path from the temporary register of the previous bit to the next bit address bus is the only extra circuitry added, which greatly simplifies the shift left circuit of the temporary register. In addition, the dedicated counter may be eliminated as a formerly idle address incrementer circuit now performs the shift left and count functions. Not only are formerly idle registers now being used for lengthy shifting and cycle counting operations, but an overall savings in chip area is recognized, since the dedicated counter is eliminated and the dedicated shifter is greatly simplified.

Abstract: An integrated circuit microcomputer with EEPROM has a limited number of modes for operation. In at least first and second modes, the inner workings of the microcomputer, including the contents of the EEPROM, can be read externally from the microcomputer. An EEPROM security bit, when set, prevents the first mode from being entered and causes the EEPROM to be erased when the second mode is entered. The EEPROM is also erased if the security bit is erased.

Abstract: A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.

Abstract: A voltage detecting circuit is disclosed having a first field effect transistor of a first type coupled in series with a second field effect transistor of a second type between a first supply voltage node and an input node, with the current channel regions coupled to the same node as the sources thereof, and the gates thereof coupled to a second supply voltage node. If the on resistance of the second transistor is significantly greater than that of the first transistor, the output node, formed by the common drains of the transistors, will be substantially the first supply voltage when the input signal is absent, and the voltage of the input signal signal when the latter is present.

Abstract: A battery powered, adaptive signal decoder is disclosed which is capable of processing detected encoded signals in accordance with a plurality of decoding schemes. The decoder has an equivalent microcomputer implementation. Energy conservation means operating independently of the detected signals acts to conserve the energy of the battery.

Abstract: A voltage translating circuit is disclosed having a first field effect transistor of a first type coupled in series with a second field effect transistor of a second type between a first supply voltage node and an input node, with the respective current channel regions thereof coupled to the same node as the sources thereof, and the gates thereof coupled to another input node. A third field effect transistor of the second type is interposed between the first and second transistors with the current channel region thereof coupled to the same node as the source region of the second transistor and the gate thereof coupled to yet another input node.

Abstract: A microcomputer system having a single step capability for use for debugging a program is provided. The microcomputer has a microprocessor which provides a load instruction signal. The load instruction signal is used to couple a software interrupt op code into the microprocessor. During the software interrupt routine, contents of registers indicating the state of the microprocessor are transferred to a stack. As the contents are being transferred they will be available on the microprocessor output bus for capture and observation. Upon completion of the software interrupt routine a return from single step instruction causes the contents of the stack to be placed back in their original registers and the program counter of the microprocessor is decremented by one so that the microprocessor can pick up the program from the point where it was interrupted.

Abstract: A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register.