Abstract: A feed-forward symbol synchronizer (200, FIG. 2) samples symbols transmitted within one or more packets that form a burst of radio frequency (RF) energy. The symbol samples (209) are delayed in a data delay buffer (214) while a phase estimate (212) is generated for each packet. A resampler (218) resamples the delayed symbol samples based on the phase estimate, resulting in resampled data (228) that includes one sample per symbol. The resampled data is clocked into a dual-port RAM (230) using a resampling clock that is also based on the phase estimate. The resampled data is then clocked out of the dual-port RAM and into a demodulator (238) using the receiver's symbol clock (232). Also described are methods of operating the feed-forward symbol synchronizer.

Abstract: A method and system for reducing the sampling rate of a signal for use with high modulation index frequency modulated signals reduces the power consumption and processing requirements of the digital signal processing equipment which performs the demodulation. In a preferred embodiment, a high modulation index FM signal is divided into in-phase and quadrature phase components by a downconverter (FIG. 1, 10). These components are sampled by analog to digital converters (20, 21) and input to a delay element (40, 41). The resulting delayed and undelayed samples are conveyed to downsamplers (60-63) where the sampling rate is reduced. The undelayed in-phase and delayed quadrature phase components are multiplied together by a first multiplier (70) while the undelayed quadrature phase and delayed in-phase components are multiplied together by a second multiplier (71).

Abstract: Crosspolarized signals of unrelated baud rates transmitted through a communication channel (10) become depolarized due to channel distortions such as rain and antenna imperfections. The resulting interference is canceled in a Modified Adaptive Crosspole Interference Canceler (MAXPIC) receiver (50, 70) by adjustment the timing in the crosspolarization path to compensate for the differential delay. Near equivalent bit error rate (BER) performance is achieved for systems utilizing crosspolarized signals with independent baud rates. In one embodiment, the receiver uses a fractionally spaced finite impulse response (FIR) filter (78) that operates at an integer multiple of the direct channel signal baud rate. In another embodiment, a variable delay (54) is used to time-align the received crosspolarized channel signal with the crosspolarization interference contained in the received direct signal.

Abstract: In a data synchronizer a timing error estimator samples a received stream of digitized data symbols at the beginning, end, and a mid-point of a symbol period. These samples are used with a model that assumes that a data stream waveform should transition along a straight line between its values at optimum sampling instances, separated by the symbol period. Differences between a mid-symbol sample estimated using this straight line model and the actual mid-symbol sample are assumed to be due to a timing error. The timing error estimator performs computations on complex inputs and therefore is compatible with a wide variety of modulation types.

Abstract: A method and apparatus for performing adaptive filtering in a high interference environment, such as for a radio, modem, or local area network. The adaptive filtering simultaneously provides interference excision while canceling resultant distortion in the signal caused by synthesizing the notch used to excise the interfering signal. An input signal (13) is pre-filtered (14) and the pre-filtered signal (15) is processed by a rejection filter (12) which combines weighted delayed versions of the pre-filtered signal (40, 42, 44, 46, 48, 50), weighted delayed versions of data decisions corresponding to the same delays as that used in the pre-filtered signal (60, 62, 64, 66, 68, 70), and a post filtered signal (27) to produce the filtered signal (19). The filtered signal (19) is processed by a data and coefficient estimator (18) to provide data decisions (25) and tap weight values (21, 23).

Abstract: In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.