Patents by Inventor Kurt B. Akeley

Kurt B. Akeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7268785
    Abstract: A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory. A central processing unit (CPU) receives a first graphics program module that outputs a first parameter referenced by a first graphics program module identifier, a second graphics program module that inputs the first parameter by referencing the first graphics program module identifier, and a first data structure that includes, in a pre-defined order, a list of first data structure identifiers. The CPU identifies a memory location in the shared memory, based on the pre-defined order of the first data structure identifiers, for one of the first data structure identifiers that is the same as the first graphics program module identifier. The CPU modifies the first and second graphics program modules to reference the first parameter by the identified memory location in the shared memory.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 11, 2007
    Assignee: NVIDIA Corporation
    Inventors: Robert Steven Glanville, Mark J. Kilgard, Kurt B. Akeley, William R. Mark
  • Patent number: 5230039
    Abstract: A graphical display system and process for specifying and controlling a display range in which a specified form of texture mapping is applied or suppressed. Object data from a host computer is processed by four pipelined graphics subsystems before being displayed on a display screen. These graphics subsystems include: 1) a Geometry Subsystem, 2) a Scan Conversion Subsystem, 3) a Raster Subsystem, and 4) a Display Subsystem. Span Processors within the Scan Conversion Subsystem manipulate pixel coordinates in order to handle sitations when coordinates are located out of range of a texture map. Processing logic and hardware registers located within each Span Processor implement two texture modes for handling out-of-range coordinates. First, a mask and comparison register is provided to hold a value specifying a selected range in which texture is applied to a pixel. If a pixel is outside the specified range, texture application is suppressed.
    Type: Grant
    Filed: February 19, 1991
    Date of Patent: July 20, 1993
    Assignee: Silicon Graphics, Inc.
    Inventors: Mark S. Grossman, Kurt B. Akeley, Robert A. Drebin