Abstract: Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Abstract: Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Abstract: Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Abstract: Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Abstract: Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Abstract: Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: A computer includes a computing display subsystem screen that includes a processor is detachably connected to the remainder of the computer. When the computing display subsystem is detached, communication may continue between the computing display subsystem and the base station using one of a plurality of techniques, including radio frequency or infrared communications.

Abstract: A flash EEPROM memory device including a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash memory device that may be used to initialize software device drivers for accessing the device, and an interface for receiving data and commands addressed to the blocks of flash EEPROM memory cells and generating signals for affecting the purpose of the commands in the flash EEPROM memory device, the interface adapted to receive a command scaled to a range of characteristics of a particular flash EEPROM memory device and respond by returning the data stored in the query memory as output depending on characteristics of the particular flash EEPROM memory device.

Abstract: A device level interface for connecting a flash EEPROM memory array to other components of a computer system which interface is designed to provide signals which directly relate to the primitive operations of a flash EEPROM memory array. The interface is adapted to use a fixed command set which allows a query command to be used to determine the functionality of the array. The values returned may be used to initialize software drivers used for accessing the array in primitives which relate to the flash EEPROM memory array.

Abstract: A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

Abstract: A storage system contains a solid state disk drive having a plurality of memory cells to store the files, including file system control information and data. In a high density mode, the solid state disk drive stores more than one bit per memory cell, and in a reliable mode, the solid state disk drive stores one bit per cell. A file configuration system stores file system control information in the reliable mode and stores data, when specified, in the high density mode. The file configuration system includes a multi-level cell extension unit that generates commands to the memory cells. A data compression unit is provided to compress file data. A block size for the data compression unit is calculated in accordance with the number of bits per cell stored in the high density mode. The file configuration system further includes an error detection and correction (EDC) unit to detect and correct data stored in the high density mode.

Abstract: A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of the array. A block write protect circuit is provided for storing block lock data to selectively lock control circuitry from accessing the array for the memory operations. The block write protect circuit locks the control circuit from accessing (1) the first block when the block write protect circuit stores a first datum of the data and (2) the second block when the block write protect circuit stores a second datum of the data. A control input is coupled to the block write protect circuit for applying a control signal to enable the block write protect circuit to lock the control circuitry in accordance with the data. The memory card further includes a register circuit coupled to the control input of each of the plurality of memories for storing a control datum to generate the control signal.

Abstract: A method for compressing a set of file structures in a flash memory subsystem is disclosed. During a clean-up operation, a sibling chain of the file structures stored in a logical block of the flash memory subsystem is traversed. If a file structure is followed by deleted file structures in the sibling chain, then the file structure is transferred to a spare logical block and the sibling pointer of the file structure is programmed bypass the deleted file structures. If a deleted file structure in the sibling chain is referenced by a previous file structure in the sibling chain, then the deleted file structure is transferred to the logical block and recycled.

Abstract: A non-volatile semiconductor memory that is erased in blocks is described. The non-volatile semiconductor memory includes an active block for storing first data and a reserve block for storing second data. The second data is a copy of the first data. The copy is made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.

Abstract: A non-volatile semiconductor memory that is erasable only in blocks is described. Each bit of the non-volatile semiconductor memory cannot be overwritten from a first logical state to a second logical state without a prior erasure. Each bit of the non-volatile semiconductor memory can be overwritten from a second logical state to a first logical state without a prior erasure. The non-volatile semiconductor memory comprises an active block for storing a first file, a reserve block for storing a second file, and a directory block. The second file is a copy of the first file. The copy is made during a clean-up operation prior to erasure of the active block. The directory block comprises a directory entry for identifying the first file.

Abstract: A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode.

Abstract: A non-volatile semiconductor memory that is erasable only in blocks is described. Each bit of the non-volatile semiconductor memory cannot be overwritten from a first logical state to a second logical state without a prior erasure. Each bit of the non-volatile semiconductor memory can be overwritten from a second logical state to a first logical state without a prior erasure. The non-volatile semiconductor memory comprises an active block for storing a first file, a reserve block for storing a second file, and a directory block. The second file is a copy of the first file. The copy is made during a clean-up operation prior to erasure of the active block. The directory block comprises a directory entry for identifying the first file.

Abstract: A computer system with power budgeting for removable devices is disclosed comprising a nonvolatile memory that contains a power resource table for storing a power consumption indication for at least one resident device for the computer system. The computer system further comprises a removable device that contains a card information structure that stores a power consumption indication for the removable device. A processor executes a power management driver that allocates a power budget to the removable device according to the power resource table and the card information structure. The power management driver updates the power: resource table to indicate the power budget to the removable device.