Patents by Inventor Kurt H. Junker
Kurt H. Junker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9780051Abstract: A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.Type: GrantFiled: December 18, 2013Date of Patent: October 3, 2017Assignee: NXP USA, Inc.Inventors: Tu-Anh N. Tran, Kurt H. Junker
-
Publication number: 20170053930Abstract: A capacitor module includes a semiconductor substrate of a first polarity. The substrate includes a deep well of a second polarity, a first well of the first polarity over the deep well, a second well of the second polarity over at least a portion of the deep well, a first capacitor including the first well as a first electrode, a dielectric layer over the first electrode, and an electrically conductive layer as a second electrode over the dielectric layer, and a second capacitor including the second well as a first electrode, a dielectric layer over the first electrode, and an electrically conductive layer as a second electrode over the dielectric layer. The first capacitor is coupled in series with the second capacitor. A metal-oxide-metal (MOM) capacitor overlays and is coupled in parallel with the first and second capacitors.Type: ApplicationFiled: August 18, 2015Publication date: February 23, 2017Inventors: ERWIN J. PRINZ, KURT H. JUNKER
-
Patent number: 9209078Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: GrantFiled: March 31, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Gregory S. Spencer, Philip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
-
Publication number: 20150171035Abstract: A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: TU-ANH N. TRAN, Kurt H. Junker
-
Publication number: 20140213050Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: GREGORY S. SPENCER, Philip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
-
Patent number: 8722530Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: GrantFiled: July 28, 2011Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
-
Publication number: 20130029485Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
-
Patent number: 8039389Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.Type: GrantFiled: February 16, 2007Date of Patent: October 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Douglas M. Reber, Mark D. Hall, Kurt H. Junker, Kyle W. Patterson, Tab Allen Stephens, Edward K. Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Irene Wright
-
Publication number: 20110210401Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
-
Patent number: 7799678Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.Type: GrantFiled: January 30, 2008Date of Patent: September 21, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Thomas J. Kropewnicki, Ritwik Chatterjee, Kurt H. Junker
-
Patent number: 7776731Abstract: A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N2/D2), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.Type: GrantFiled: September 14, 2007Date of Patent: August 17, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kurt H. Junker, Tien-Ying Luo, Dina H. Triyoso
-
Patent number: 7700499Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.Type: GrantFiled: January 11, 2008Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
-
Patent number: 7678665Abstract: A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.Type: GrantFiled: March 7, 2007Date of Patent: March 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Michael D. Turner, Suresh Venkatesan, Kurt H. Junker
-
Patent number: 7678698Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.Type: GrantFiled: May 4, 2007Date of Patent: March 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Xiangzheng Bo, Tien Ying Luo, Kurt H. Junker, Paul A. Grudowski, Venkat R. Kolagunta
-
Patent number: 7579228Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.Type: GrantFiled: July 10, 2007Date of Patent: August 25, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Paul A. Grudowski, Kurt H. Junker, Thomas J. Kropewnicki, Andrew G. Nagy
-
Publication number: 20090191708Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: Thomas J. Kropewnicki, Ritwik Chatterjee, Kurt H. Junker
-
Publication number: 20090075434Abstract: A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N2/D2), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Inventors: Kurt H. Junker, Tien-Ying Luo, Dina H. Triyoso
-
Publication number: 20090017587Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.Type: ApplicationFiled: July 10, 2007Publication date: January 15, 2009Inventors: Paul A. Grudowski, Kurt H. Junker, Thomas J. Kropewnicki, Andrew G. Nagy
-
Publication number: 20080272411Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.Type: ApplicationFiled: May 4, 2007Publication date: November 6, 2008Inventors: Xiangzheng Bo, Tien Ying Luo, Kurt H. Junker, Paul A. Grudowski, Venkat R. Kolagunta
-
Publication number: 20080220617Abstract: A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.Type: ApplicationFiled: March 7, 2007Publication date: September 11, 2008Inventors: Michael D. Turner, Suresh Venkatesan, Kurt H. Junker