Abstract: A parallel operation linear feedback shift-register (LFSR) that generates random test patterns or creates a signature that represents the response of a device under test at ultra high speed using low speed components and/or a slow rate clock. The apparatus is comprised of: a register connected to an external clock, and a plurality of combinatorial logic networks sequentially connected, the last of which drives the register which in turn feeds back into the first of the combinatorial logic networks. Each of the combinatorial networks provides a pseudo-random pattern which are then outputted in parallel, thereby creating a high speed data flow. By providing additional data inputs to the combinatorial networks, the pseudo-random patterns become the signature of the input data.

Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2.sup.M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin.