Patents by Inventor Kushal D. Murthy
Kushal D. Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996830Abstract: One example described herein includes a power switch control system. The system includes a first monitoring terminal coupled to a first terminal of a power transistor and a second monitoring terminal coupled to a second terminal of the power transistor. The power transistor and the power switch control system can form an ideal diode between the first monitoring terminal arranged as an anode and the second monitoring terminal arranged as a cathode. The system further includes a reverse current controller coupled to the first monitoring terminal and the second monitoring terminal and is configured to control activation of the power transistor to conduct a reverse current from the second monitoring terminal to the first monitoring terminal in response to a reverse voltage arranged as a cathode voltage at the second monitoring terminal being greater than an anode voltage at the first monitoring terminal.Type: GrantFiled: October 29, 2021Date of Patent: May 28, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kushal D. Murthy, Subrato Roy, Dilip Kumar Jain, Abhijeet Gopal Godbole
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Publication number: 20220352885Abstract: One example described herein includes a power switch control system. The system includes a first monitoring terminal coupled to a first terminal of a power transistor and a second monitoring terminal coupled to a second terminal of the power transistor. The power transistor and the power switch control system can form an ideal diode between the first monitoring terminal arranged as an anode and the second monitoring terminal arranged as a cathode. The system further includes a reverse current controller coupled to the first monitoring terminal and the second monitoring terminal and is configured to control activation of the power transistor to conduct a reverse current from the second monitoring terminal to the first monitoring terminal in response to a reverse voltage arranged as a cathode voltage at the second monitoring terminal being greater than an anode voltage at the first monitoring terminal.Type: ApplicationFiled: October 29, 2021Publication date: November 3, 2022Inventors: KUSHAL D. MURTHY, SUBRATO ROY, DILIP KUMAR JAIN, ABHIJEET GOPAL GODBOLE
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Patent number: 11243235Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.Type: GrantFiled: December 21, 2018Date of Patent: February 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhaskar Ramachandran, Kushal D. Murthy, Aalok Dyuti Saha
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Patent number: 10838016Abstract: In described examples, a circuit includes a first driver. The first driver is coupled to a first node, and the first node is coupled to an output pin. A second driver is coupled to a second node, and the second node is coupled to a first voltage terminal. A comparator is coupled to the first node and the second node. A sustaining driver is coupled to the comparator and provides a threshold current to each of the first node and the second node when a short is detected at the output pin.Type: GrantFiled: May 10, 2019Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhaskar Ramachandran, Kushal D. Murthy
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Patent number: 10784829Abstract: A circuit includes a power transistor including a first control input and first and second current terminals, the second current terminal to be coupled to a load to provide current to the load. A second transistor includes a second control input and third and fourth current terminals, and the first and second control inputs connected together and the first and third current terminals connected together. A third transistor includes a third control input and fifth and sixth current terminals. A fourth transistor includes a fourth control input and seventh and eighth current terminals, and the seventh current terminal is coupled to the fourth and fifth current terminals. An amplifier amplifies a difference between voltages on the second and fourth current terminals. An output of the amplifier is coupled to the third control input and a diode device is connected between the third and fourth control inputs.Type: GrantFiled: December 17, 2018Date of Patent: September 22, 2020Assignee: Texas Instruments IncorporatedInventors: Dattatreya Baragur Suryanarayana, Kushal D Murthy
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Publication number: 20200014350Abstract: A circuit includes a power transistor including a first control input and first and second current terminals, the second current terminal to be coupled to a load to provide current to the load. A second transistor includes a second control input and third and fourth current terminals, and the first and second control inputs connected together and the first and third current terminals connected together. A third transistor includes a third control input and fifth and sixth current terminals. A fourth transistor includes a fourth control input and seventh and eighth current terminals, and the seventh current terminal is coupled to the fourth and fifth current terminals. An amplifier amplifies a difference between voltages on the second and fourth current terminals. An output of the amplifier is coupled to the third control input and a diode device is connected between the third and fourth control inputs.Type: ApplicationFiled: December 17, 2018Publication date: January 9, 2020Inventors: Dattatreya BARAGUR SURYANARAYANA, Kushal D MURTHY
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Publication number: 20200011917Abstract: In described examples, a circuit includes a first driver. The first driver is coupled to a first node, and the first node is coupled to an output pin. A second driver is coupled to a second node, and the second node is coupled to a first voltage terminal. A comparator is coupled to the first node and the second node. A sustaining driver is coupled to the comparator and provides a threshold current to each of the first node and the second node when a short is detected at the output pin.Type: ApplicationFiled: May 10, 2019Publication date: January 9, 2020Inventors: Bhaskar RAMACHANDRAN, Kushal D. MURTHY
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Publication number: 20200011906Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.Type: ApplicationFiled: December 21, 2018Publication date: January 9, 2020Inventors: Bhaskar RAMACHANDRAN, Kushal D. MURTHY, Aalok Dyuti SAHA
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Patent number: 10459030Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.Type: GrantFiled: October 19, 2017Date of Patent: October 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kushal D Murthy, Manish Parmar, Preetam Tadeparthy, Muthusubramanian Venkateswaran
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Patent number: 10297334Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.Type: GrantFiled: May 17, 2017Date of Patent: May 21, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anindita Borah, Muthusubramanian Venkateswaran, Kushal D. Murthy, Vikram Gakhar, Preetam Tadeparthy
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Patent number: 10177644Abstract: A voltage converter includes a high side power transistor coupled to an input voltage node and a low side power transistor coupled to the high side power transistor at a switch node. The switch node is configured to be coupled to an inductor. A slope detector circuit is configured to receive a signal indicative of a current through the inductor. The inductor current is a triangular waveform comprising a ramp-up phase and a ramp-down phase. The slope detector circuit also is configured to generate an output signal encoding when the inductor current is ramping up and when the inductor current is ramping down.Type: GrantFiled: October 10, 2017Date of Patent: January 8, 2019Assignee: Texas Instruments IncorporatedInventors: Kushal D. Murthy, Vikram Gakhar, Muthusubramanian Venkateswaran, Preetam Tadeparthy
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Publication number: 20180038913Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.Type: ApplicationFiled: October 19, 2017Publication date: February 8, 2018Inventors: Kushal D Murthy, Manish Parmar, Preetam Tadeparthy, Muthusubramanian Venkateswaran
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Publication number: 20170337985Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.Type: ApplicationFiled: May 17, 2017Publication date: November 23, 2017Inventors: Anindita BORAH, Muthusubramanian VENKATESWARAN, Kushal D. MURTHY, Vikram GAKHAR, Preetam TADEPARTHY
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Patent number: 9823306Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.Type: GrantFiled: February 11, 2016Date of Patent: November 21, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kushal D Murthy, Manish Parmar, Preetam Tadeparthy, Muthusubramanian Venkateswaran
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Publication number: 20170234926Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.Type: ApplicationFiled: February 11, 2016Publication date: August 17, 2017Inventors: Kushal D. Murthy, Manish Parmar, Preetam Tadeparthy, Muthusubramanian Venkateswaran