Patents by Inventor Kwai Hong Wong
Kwai Hong Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190259731Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.Type: ApplicationFiled: April 29, 2019Publication date: August 22, 2019Applicant: Unisem (M) BerhadInventors: Kim Heng Tan, Chan Wah Chai, Kwai Hong Wong
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Publication number: 20190181095Abstract: A method is disclosed for manufacturing a discrete package for housing at least one integrated circuit die with electromagnetic interference shielding. The method may utilize a lead frame with a central die paddle and outwardly extending leads. The die paddle may have a top surface and an opposing bottom surface. The method may also have at least one integrated circuit die with a top surface and an opposing bottom surface. The integrated circuit die may be attached to the top surface of the die paddle. At least one conductive material bond may be established between the lead frame and the integrated circuit die. A dielectric material over mold may encapsulate the integrated circuit die and lead frame. A second dielectric material over mold may encapsulate the integrated circuit die and the lead frame. Further, a conductive coating may encapsulate the top and side surfaces of the package.Type: ApplicationFiled: December 8, 2017Publication date: June 13, 2019Applicant: Unisem (M) BerhadInventors: Kwai Hong Wong, Wai Kuen Lam
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Publication number: 20180130768Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.Type: ApplicationFiled: January 5, 2017Publication date: May 10, 2018Applicant: Unisem (M) BerhadInventors: Kim Heng Tan, Chan Wah Chai, Kwai Hong Wong
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Publication number: 20180130720Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, grinding a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Applicant: Unisem (M) BerhadInventors: Kim Heng Tan, Chan Wah Chai, Kwai Hong Wong
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Publication number: 20180130769Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.Type: ApplicationFiled: August 11, 2017Publication date: May 10, 2018Applicant: Unisem (M) BerhadInventors: Kim Heng Tan, Chan Wah Chai, Kwai Hong Wong
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Patent number: 8664753Abstract: A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices.Type: GrantFiled: November 25, 2009Date of Patent: March 4, 2014Assignee: Infineon Technologies AGInventors: Teck Sim Lee, Chee Voon Tan, Kwai Hong Wong
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Patent number: 8334586Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.Type: GrantFiled: May 18, 2011Date of Patent: December 18, 2012Assignee: Infineon Technologies AGInventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Soon Hock Tong, Kwai Hong Wong
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Publication number: 20110215460Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.Type: ApplicationFiled: May 18, 2011Publication date: September 8, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Soon Hock Tong, Kwai Hong Wong
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Patent number: 7969018Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.Type: GrantFiled: July 15, 2008Date of Patent: June 28, 2011Assignee: Infineon Technologies AGInventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Soon Hock Tong, Kwai Hong Wong
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Publication number: 20110121439Abstract: A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices.Type: ApplicationFiled: November 25, 2009Publication date: May 26, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Teck Sim Lee, Chee Voon Tan, Kwai Hong Wong
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Publication number: 20100013106Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.Type: ApplicationFiled: July 15, 2008Publication date: January 21, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Soon Hock Tong, Kwai Hong Wong