Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.

Abstract: A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

Abstract: A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages.

Abstract: A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Abstract: A semiconductor device includes a plurality of stacked dies electrically connected with each other. Each of the stacked dies includes a data path, a strobe path, a stack information generation circuit, and a delay control circuit. The data path transmits a data signal. The strobe path transmits a data strobe signal. The stack information generation circuit generates stack information representing a number of the dies. The delay control circuit controls a delay time of at least one of the data path and the strobe path based on the stack information.

Abstract: A semiconductor device includes a plurality of stacked dies electrically connected with each other. Each of the stacked dies includes a data path, a strobe path, a stack information generation circuit, and a delay control circuit. The data path transmits a data signal. The strobe path transmits a data strobe signal. The stack information generation circuit generates stack information representing a number of the dies. The delay control circuit controls a delay time of at least one of the data path and the strobe path to based on the stack information.

Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.

Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.