Abstract: Provided are a repeater device for a DisplayPort side channel and an operating method thereof. The repeater device of a DisplayPort includes: a source device processor transmits or receives an electrical signal of a side channel data of the display port to or from a source device and processes repeater data; and a sink device processor transmits or receives an electrical signal of a side channel data of the display port to or from a sink device and processes repeater data, wherein the source device processor or the sink device processor comprising a controller processes repeating of the side channel data of the display port using the repeater data which is obtained by transforming the electrical signal to an optical signal.

Abstract: Provided are a repeater device for a DisplayPort side channel and an operating method thereof. The repeater device of a DisplayPort includes: a source device processor transmits or receives an electrical signal of a side channel data of the display port to or from a source device and processes repeater data; and a sink device processor transmits or receives an electrical signal of a side channel data of the display port to or from a sink device and processes repeater data, wherein the source device processor or the sink device processor comprising a controller processes repeating of the side channel data of the display port using the repeater data which is obtained by transforming the electrical signal to an optical signal.

Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Abstract: The inventive concept relates to a supply regulated voltage controlled oscillator having a function of an active loop filter by sharing one operational amplifier without additional use of active elements in a supply regulated voltage controlled oscillator using an operational amplifier as a supply regulator, and a phase locked loop using the same.

Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

Abstract: The inventive concept relates to a supply regulated voltage controlled oscillator having a function of an active loop filter by sharing one operational amplifier without additional use of active elements in a supply regulated voltage controlled oscillator using an operational amplifier as a supply regulator, and a phase locked loop using the same.

Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.