Patents by Inventor Kwang Hong Tan

Kwang Hong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertically structured pad system
    Patent number: 11296019
    Abstract: A vertically structured pad system and method can include: a platform having etch attributes, a platform top surface, and a platform side surface; a structure on the platform, the structure including a structure side surface extended up from the platform top surface terminating in a structure top surface, the structure including a structure interior surface defining a cavity within the structure, and the platform top surface exposed from within the cavity; and an interconnect structure adhered to the platform and the structure, the interconnect structure conforming with an exterior shape of the platform side surface in combination with the structure for locking the interconnect structure onto the platform and the structure.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 5, 2022
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kwang Hong Tan, Mihalis Kolios Michael, David Alan Pruitt
  • Power management application of interconnect substrates
    Patent number: 10748845
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 18, 2020
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • POWER MANAGEMENT APPLICATION OF INTERCONNECT SUBSTRATES
    Publication number: 20190341344
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 7, 2019
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • Power management application of interconnect substrates
    Patent number: 10332827
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 25, 2019
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony J. Stratakos
  • POWER MANAGEMENT APPLICATION OF INTERCONNECT SUBSTRATES
    Publication number: 20170125335
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Application
    Filed: December 9, 2016
    Publication date: May 4, 2017
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony J. Stratakos
  • Power management applications of interconnect substrates
    Patent number: 9520342
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 13, 2016
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • POWER MANAGEMENT APPLICATIONS OF INTERCONNECT SUBSTRATES
    Publication number: 20150303132
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Application
    Filed: June 29, 2015
    Publication date: October 22, 2015
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • Power management applications of interconnect substrates
    Patent number: 9099340
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 4, 2015
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • BOC BGA package for die with I-shaped bond pad layout
    Patent number: 7112048
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • BOC BGA package for die with I-shaped bond pad layout
    Patent number: 6720666
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: April 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • BOC BGA package for die with I-shaped bond pad layout
    Patent number: 6692987
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • BOC BGA package for die with I-shaped bond pad layout
    Publication number: 20030211660
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 13, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • BOC BGA package for die with I-shaped bond pad layout
    Publication number: 20030211659
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 13, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • BOC BGA package for die with I-shaped bond pad layout
    Publication number: 20030148557
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 7, 2003
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang