Abstract: A method for encoding a channel using a parallel convolutional encoder is disclosed. The method includes the steps of a first step for performing an encoding operation using a parallel convolutional encoder at the time when a data is inputted into a frame input data register for implementing a channel encoding operation and generating a code symbol, and a second step for storing the thusly generated code symbol into an interleaver RAM which is alternately selected by the frame unit.

Abstract: A method for encoding a digital communication channel is disclosed. The method includes the steps of first storing a frame data, which is inputted for a channel encoding operation, into an encoder RAM (ERAM0); second addressing the ERAM and storing the data into a register via a multiplexer in accordance with a control of a frame selection signal; third addressing the ERAM for reading the previous input data and storing the read data into the register; fourth selecting an input data among two register output data, inputting the selected input data into the convolutional encoder and generating a code symbol; and fifth selecting one among the code symbols and obtaining an output of the channel encoder that completed the convolutional encoding and interleaving operations.

Abstract: A high speed ROM-based Nyquist FIR filter which is capable of enhancing a modulation speed without increasing the operational frequency of the filter by overcoming the problems encountered in the conventional digital modulation ROM-based FIR filter. Therefore, it is possible to increase the modulation speed by the interpolation ratio without increasing the operational frequency of the filter compared to the method of using a conventional FIR filter using one ROM. Accordingly, the high speed ROM-based Nyquist FIR filter according to the present invention is well adaptive to the modulation FIR filter of a broadband digital communication which requires a high speed data processing capability.

Abstract: A hadamard code generation circuit is disclosed. The circuit includes a start reset signal generator for generating a start reset signal START.sub.-- RESET when a 6-bit output signal REF.sub.-- C from the 6-bit reference counter, a higher 4-bit index output signal H(5:2) of the 6-bit register and a 2-bit value from a ground circuit are identical; a "0" value force allocation unit for outputting a FORCE.sub.-- 0.sub.-- DEL signal for forcibly allocating all values of the 0th column to "0" when a 4-bit output signal REF.sub.-- C (5:2) from the 6-bit reference counter and a 4-bit value from the ground circuit are identical; a 2-bit counter for receiving the start reset signal and an external clock signal, outputting lowest bit signals C1 and C0 and outputting a carry-out signal; a 4-bit counter operated in accordance with a result that an inverted FORCE.sub.

Abstract: In case microcontroller and digital signal processing blocks are used together in one chip, there has been a problem in which the synchronization of the clocks are not consistent with each other when sending a signal from one block to another. In addition, when a reference clock is activated during a change of input signal, an incomplete interval has occurred. Accordingly, in order to solve the above mentioned problem, the present invention discloses a synchronizing circuit which uses a latch circuit("RS") consisted of NAND gates to synchronize an asynchronous input data and a reference clock, thereby solving the problem in which an incomplete interval occurs.

Abstract: The present invention relates in general to a channel CODEC to increase the transmitting effect on a communication channel of a communication system, and more specifically to a branch metric module of a viterbi decoder. The module includes an operator for operating and outputting the differential magnitude of two signals, one signal being a code word generated to perform the viterbi decode and the other being a signal transmitted through the channel. An adder sums and outputs the data which is outputted to it from the operator. A receiving code word converter converts the magnitude of any of bits by the linear sampling quantization process, and non-linearly converts it in accordance with a preestimated or predetermined format. A number of operators calculate the magnitude between two signals at the absolute value to convert the magnitude of an inputted generative code word and the magnitude of the non-linear converted receiving code word.