Patents by Inventor Kwang Jin Na
Kwang Jin Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948631Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phis change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.Type: GrantFiled: May 7, 2021Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae Hui Na, Mu Hui Park, Kwang Jin Lee, Yong Jun Lee
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Publication number: 20170148497Abstract: A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory.Type: ApplicationFiled: February 2, 2017Publication date: May 25, 2017Inventor: Kwang Jin NA
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Patent number: 9659905Abstract: A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller.Type: GrantFiled: March 25, 2015Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Kyu Bong Kong, Kwang Jin Na
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Patent number: 9601173Abstract: A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory.Type: GrantFiled: March 30, 2015Date of Patent: March 21, 2017Assignee: SK Hynix Inc.Inventor: Kwang Jin Na
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Patent number: 9496878Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.Type: GrantFiled: December 13, 2012Date of Patent: November 15, 2016Assignee: SK Hynix Inc.Inventors: Hae-Rang Choi, Joo-Hwan Cho, Kwang-Jin Na, Kwan-Dong Kim
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Publication number: 20160147250Abstract: A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller.Type: ApplicationFiled: March 25, 2015Publication date: May 26, 2016Inventors: Kyu Bong KONG, Kwang Jin NA
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Patent number: 9281051Abstract: A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address.Type: GrantFiled: October 17, 2014Date of Patent: March 8, 2016Assignee: SK Hynix Inc.Inventors: Kyu Bong Kong, Kwang Jin Na
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Patent number: 9270285Abstract: Semiconductor chips are provided. The semiconductor chip includes a selection phase clock generator and a data input/output portion. The selection phase clock generator is configured to receive an external clock signal and an inversed external clock signal to generate phase clock signals, configured to receive a first external test clock signal and a second external test clock signal to generate test phase clock signals, and configured to output the phase clock signals or the test phase clock signals as selection phase clock signals in response to a test mode signal.Type: GrantFiled: July 17, 2013Date of Patent: February 23, 2016Assignee: SK Hynix Inc.Inventors: Tae Wook Kang, Kwang Jin Na
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Publication number: 20150380075Abstract: A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address.Type: ApplicationFiled: October 17, 2014Publication date: December 31, 2015Inventors: Kyu Bong KONG, Kwang Jin NA
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Publication number: 20150206563Abstract: A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory.Type: ApplicationFiled: March 30, 2015Publication date: July 23, 2015Inventor: Kwang Jin NA
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Patent number: 9077438Abstract: A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal.Type: GrantFiled: November 12, 2013Date of Patent: July 7, 2015Assignee: SK Hynix Inc.Inventors: Tae-Wook Kang, Kwang-Jin Na
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Patent number: 9030907Abstract: A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device.Type: GrantFiled: December 15, 2013Date of Patent: May 12, 2015Assignee: SK Hynix Inc.Inventors: Kwang-Jin Na, Tae-Wook Kang
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Publication number: 20150098296Abstract: A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device.Type: ApplicationFiled: December 15, 2013Publication date: April 9, 2015Applicant: SK hynix Inc.Inventors: Kwang-Jin NA, Tae-Wook KANG
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Publication number: 20150043627Abstract: A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal.Type: ApplicationFiled: November 12, 2013Publication date: February 12, 2015Applicant: SK hynix Inc.Inventors: Tae-Wook KANG, Kwang-Jin NA
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Patent number: 8829960Abstract: The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.Type: GrantFiled: November 27, 2012Date of Patent: September 9, 2014Assignee: SK Hynix Inc.Inventor: Kwang-Jin Na
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Publication number: 20140056085Abstract: Semiconductor chips are provided. The semiconductor chip includes a selection phase clock generator and a data input/output portion. The selection phase clock generator is configured to receive an external clock signal and an inversed external clock signal to generate phase clock signals, configured to receive a first external test clock signal and a second external test clock signal to generate test phase clock signals, and configured to output the phase clock signals or the test phase clock signals as selection phase clock signals in response to a test mode signal.Type: ApplicationFiled: July 17, 2013Publication date: February 27, 2014Applicant: SK hynix Inc.Inventors: Tae Wook KANG, Kwang Jin NA
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Publication number: 20140021990Abstract: The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.Type: ApplicationFiled: November 27, 2012Publication date: January 23, 2014Applicant: SK HYNIX INC.Inventor: Kwang-Jin NA
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Publication number: 20130321050Abstract: A delay-locked loop to control a delay amount of an external clock based on phase comparisons of a feedback clock acquired by delaying a DLL clock and the external clock and generate the DLL clock includes first and second delay units, a phase mixing unit and a slew rate control unit. The first delay unit increases the delay amount of the external clock through short and long delay elements, and generates a first delayed clock. The second delay unit increases the delay amount of the external clock through short and long delay elements, and generates a second delayed clock. The phase mixing unit mixes phases of the first and second delayed clocks. The slew rate control unit increases electrical load of the first and second delayed clocks when the delay amount of the external clock is controlled through the long delay elements of the first delay unit.Type: ApplicationFiled: December 7, 2012Publication date: December 5, 2013Applicant: SK hynix Inc.Inventor: Kwang Jin NA
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Publication number: 20130294186Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.Type: ApplicationFiled: December 13, 2012Publication date: November 7, 2013Applicant: SK HYNIX INC.Inventors: Hae-Rang CHOI, Joo-Hwan CHO, Kwang-Jin NA, Kwan-Dong KIM
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Patent number: 8514639Abstract: A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock.Type: GrantFiled: December 30, 2010Date of Patent: August 20, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kwang-Jin Na