Patents by Inventor Kwang Kee Chae

Kwang Kee Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8841198
    Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: September 23, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Hwan Kim, Kwang Kee Chae, Jong Goo Jung, Ok Min Moon, Young Bang Lee, Sung Eun Park
  • Patent number: 8007594
    Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: August 30, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young Bang Lee, Kwang Kee Chae, Ok Min Moon
  • Patent number: 7923784
    Abstract: A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: April 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang Kee Chae, Jae Seon Yu, Jae Kyun Lee
  • Publication number: 20110023907
    Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.
    Type: Application
    Filed: July 12, 2010
    Publication date: February 3, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young Bang LEE, Kwang Kee CHAE, Ok Min MOON
  • Patent number: 7855109
    Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: December 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Hwan Kim, Kwang Kee Chae, Jong Goo Jung, Ok Min Moon, Young Bang Lee, Sung Eun Park
  • Publication number: 20100164051
    Abstract: A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 1, 2010
    Inventors: Kwang Kee CHAE, Jae Seon YU, Jae Kyun LEE
  • Publication number: 20100159683
    Abstract: A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom
    Type: Application
    Filed: June 29, 2009
    Publication date: June 24, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jin Yul Lee, Bong Ho Choi, Kwang Kee Chae, Dong Seok Kim, Jae Seon Yu, Hyung Hwan Kim, Jae Kyun Lee
  • Publication number: 20100151656
    Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is
    Type: Application
    Filed: December 30, 2008
    Publication date: June 17, 2010
    Inventors: Hyung Hwan KIM, Kwang Kee CHAE, Jong Goo JUNG, Ok Min MOON, Young Bang LEE, Sung Eun PARK
  • Publication number: 20090267199
    Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 29, 2009
    Inventors: Hyung Hwan KIM, Kwang Kee CHAE, Jong Goo JUNG, Ok Min MOON, Young Bang LEE, Sung Eun PARK
  • Publication number: 20080003792
    Abstract: A gate of a semiconductor device is formed by forming sequentially a gate insulation layer, a polysilicon layer, metal based layer and a hard mask on a semiconductor substrate; etching primarily the metal based layer and a partial thickness of the polysilicon layer using the hard mask as an etch mask; cleaning primarily surfaces of the etched metal based layer and polysilicon layer with an HF-containing solution; and cleaning secondarily the primarily cleaned surfaces using ozone.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Inventor: Kwang Kee Chae