Abstract: In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

Abstract: In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

Abstract: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.

Abstract: An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

Abstract: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.

Abstract: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.

Abstract: An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

Abstract: Methods of fabricating a semiconductor memory device include forming a plurality of memory cells in a cell region of a semiconductor substrate. An insulating layer is formed on the plurality of memory cells in the cell region and on a peripheral circuit region of the substrate, and a bit line contact plug is formed extending through the insulating layer to the substrate in the cell region. A continuous conductive layer is formed on the insulating layer in the cell region and the peripheral circuit region. The continuous conductive layer is patterned to define a bit line contact pad on the bit line contact plug in the cell region and at least one fuse in the peripheral circuit region, for example, using a same mask pattern. The continuous conductive layer may also be patterned to define a load resistor in the peripheral circuit region. Related devices are also discussed.

Abstract: An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

Abstract: A trench isolation region can be formed in a device substrate by planarizing a first insulation layer in a trench of a substrate using chemical mechanical polishing so that the first insulation layer is removed from a surface of the substrate outside the trench and remains inside the trench, thereby forming an opening to a void beneath a surface of the first insulation layer. A further portion of the first insulation layer can be removed from inside the trench using a wet etch or a dry etch process to increase the opening to the void. A second insulation layer can be deposited in the void in the first insulation layer through the increased opening.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.

Abstract: A method according to some embodiments of the invention includes sequentially forming first and second conductive layers, patterning the second conductive layer to form second conductive patterns, and forming a mask pattern connecting the second conductive patterns. Using the mask pattern and the second conductive patterns as an etching mask, the first conductive layer is etched to form a first conductive pattern electrically connecting the second conductive patterns. Before the second conductive layer is formed, a gate interlayer insulating layer including at least two openings exposing a top surface of the first conductive layer may be formed. The second conductive patterns are in contact with top surfaces of the first conductive pattern. During formation of the second conductive patterns, a dummy pattern may be formed on the gate interlayer insulating layer and spaced apart from the second conductive patterns.

Abstract: A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.

Abstract: A method of fabricating a non-volatile memory device having a U-shaped floating gate is described. This method forms a device isolation layer in a predetermined region of a semiconductor substrate, thereby defining at least one active region. A floating gate pattern covering active regions and having a gap region exposing the device isolation layer therebetween is formed, and an insulation material pattern where the width of a projection is wider than an upper width of the gap region while the projection covers the gap region and is higher then an upper surface of the floating gate pattern is formed. Subsequently, the floating gate pattern is etched using the insulation material pattern, thereby forming a modified floating gate pattern showing a U-shaped cross section on an active region. As a result, a coupling ratio of the non-volatile memory device can be increased.

Abstract: A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed over the conductive layer. Next, a photoresist pattern is formed over the hard mask layer. The hard mask layer is etched to form a hard mask pattern, using the photoresist pattern as an etching mask. The upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact, using the photoresist pattern as an etching mask. The slope-etched upper portion of the conductive layer is again vertically etched and the lower portion of the conductive layer is concurrently slope-etched, using the hard pattern as an etching mask. With the present invention, a bridge between floating gates can be reduced, and field loss can be reduced during processing steps such as an ONO etching process.

Abstract: A method of fabricating a non-volatile memory device having a U-shaped floating gate is described. This method forms a device isolation layer in a predetermined region of a semiconductor substrate, thereby defining at least one active region. A floating gate pattern covering active regions and having a gap region exposing the device isolation layer therebetween is formed, and an insulation material pattern where the width of a projection is wider than an upper width of the gap region while the projection covers the gap region and is higher then an upper surface of the floating gate pattern is formed. Subsequently, the floating gate pattern is etched using the insulation material pattern, thereby forming a modified floating gate pattern showing a U-shaped cross section on an active region. As a result, a coupling ratio of the non-volatile memory device can be increased.