Patents by Inventor Kwun-Soo Cheon
Kwun-Soo Cheon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8310881Abstract: Disclosed are a semiconductor device capable of testing memory cells and a test method. The semiconductor device includes a plurality of terminals, each terminal being configured to receive similar data during a test mode, a plurality of buffers, each buffer being configured to receive data from a corresponding terminal and output either the data or changed data to a corresponding memory cells in response to a control signal, and a control unit configured to generate a plurality of control signals, each control signal being respectively applied to a corresponding buffer.Type: GrantFiled: April 2, 2010Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Joung-wook Moon, Kwun-soo Cheon, Jung-sik Kim
-
Patent number: 7941714Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.Type: GrantFiled: January 3, 2008Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hwan Cho, Kwun-soo Cheon, Hyun-soon Jang, Seung-whan Seo
-
Publication number: 20100254196Abstract: Disclosed are a semiconductor device capable of testing memory cells and a test method. The semiconductor device includes a plurality of terminals, each terminal being configured to receive similar data during a test mode, a plurality of buffers, each buffer being configured to receive data from a corresponding terminal and output either the data or changed data to a corresponding memory cells in response to a control signal, and a control unit configured to generate a plurality of control signals, each control signal being respectively applied to a corresponding buffer.Type: ApplicationFiled: April 2, 2010Publication date: October 7, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joung-wook MOON, Kwun-soo CHEON, Jung-sik KIM
-
Patent number: 7783944Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad and a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.Type: GrantFiled: December 14, 2007Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kwun-soo Cheon, Chang-yong Lee, Won-kyung Chung
-
Patent number: 7764562Abstract: A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit is initialized in response to the column reset signal. The semiconductor memory device can reduce a peak value of a surge current by initializing a row path circuit and a column path circuit at different time points. Therefore, the semiconductor memory device may have a relatively short setup time of an internal power supply voltage.Type: GrantFiled: February 1, 2008Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kwun-Soo Cheon, Byong-Wook Na
-
Patent number: 7457179Abstract: A semiconductor memory device includes a plurality of address pads, a plurality of DQ pads, an address buffer, a data input buffer, a latch circuit and a first delay circuit. The address buffer receives a plurality of first address signals through the address pads and buffers the first address signals to generate a plurality of second address signals. The data input buffer receives one of a plurality of input data through the DQ pads and buffers the input data to generate a first data or receives the first address signals through the DQ pads and buffers the address signals to generate a plurality of third address signals. The latch circuit latches the third address signals to generate fourth address signals in response to a test mode control signal. The first delay circuit selects the second address signals or the fourth address signals and delays the selected address signals for a predetermined time to generate fifth address signals.Type: GrantFiled: January 5, 2007Date of Patent: November 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Kwun-Soo Cheon
-
Patent number: 7449917Abstract: A level shifting circuit for a semiconductor device comprises a controller, a level shifting portion, and a driving portion. The controller is adapted to level shift a power converting input signal having a first voltage level to generate a pair of control signals having different logic levels from each other. One of the pair of control signals has a second voltage level that is different from the first level. The level shifting portion is adapted to level shift an input signal having the first voltage level to generate a level shifter output signal having the second voltage level or a third voltage level depending on the respective logic levels of the pair of control signals. The driving portion is adapted to drive an output signal with the second or third voltage level based on the voltage level of the level shifter output signal.Type: GrantFiled: November 30, 2006Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Kwun-Soo Cheon
-
Publication number: 20080186792Abstract: A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit is initialized in response to the column reset signal. The semiconductor memory device can reduce a peak value of a surge current by initializing a row path circuit and a column path circuit at different time points. Therefore, the semiconductor memory device may have a relatively short setup time of an internal power supply voltage.Type: ApplicationFiled: February 1, 2008Publication date: August 7, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Kwun-Soo Cheon, Byong-Wook Na
-
Publication number: 20080165596Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad and a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.Type: ApplicationFiled: December 14, 2007Publication date: July 10, 2008Inventors: Kwun-soo Cheon, Chang-yong Lee, Won-kyung Chung
-
Publication number: 20080168316Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.Type: ApplicationFiled: January 3, 2008Publication date: July 10, 2008Inventors: Yong-hwan Cho, Kwun-soo Cheon, Hyun-soon Jang, Seung-whan Seo
-
Patent number: 7319626Abstract: A first pump circuit is coupled to a first pump signal line and is configured to generate a first voltage greater than a power supply voltage at an output thereof responsive to transition of the first pump signal line from a ground voltage to the power supply voltage. A second pump circuit includes a first switching circuit configured to couple a first capacitor between the output of the first pump circuit and a ground voltage node responsive to the transition of a first pump signal line from the ground voltage to the power supply voltage to charge the first capacitor to the first voltage, and to couple a second capacitor between the first capacitor and a second pump signal line responsive to a transition of the second pump signal line from the ground voltage to the power supply voltage to generate a second voltage greater than the first voltage.Type: GrantFiled: January 10, 2006Date of Patent: January 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Kwun-Soo Cheon
-
Publication number: 20070262790Abstract: A level shifting circuit for a semiconductor device comprises a controller, a level shifting portion, and a driving portion. The controller is adapted to level shift a power converting input signal having a first voltage level to generate a pair of control signals having different logic levels from each other. One of the pair of control signals has a second voltage level that is different from the first level. The level shifting portion is adapted to level shift an input signal having the first voltage level to generate a level shifter output signal having the second voltage level or a third voltage level depending on the respective logic levels of the pair of control signals. The driving portion is adapted to drive an output signal with the second or third voltage level based on the voltage level of the level shifter output signal.Type: ApplicationFiled: November 30, 2006Publication date: November 15, 2007Inventor: Kwun-Soo Cheon
-
Publication number: 20070171759Abstract: A semiconductor memory device includes a plurality of address pads, a plurality of DQ pads, an address buffer, a data input buffer, a latch circuit and a first delay circuit. The address buffer receives a plurality of first address signals through the address pads and buffers the first address signals to generate a plurality of second address signals. The data input buffer receives one of a plurality of input data through the DQ pads and buffers the input data to generate a first data or receives the first address signals through the DQ pads and buffers the address signals to generate a plurality of third address signals. The latch circuit latches the third address signals to generate fourth address signals in response to a test mode control signal. The first delay circuit selects the second address signals or the fourth address signals and delays the selected address signals for a predetermined time to generate fifth address signals.Type: ApplicationFiled: January 5, 2007Publication date: July 26, 2007Inventor: Kwun-Soo Cheon
-
Publication number: 20060176103Abstract: A first pump circuit is coupled to a first pump signal line and is configured to generate a first voltage greater than a power supply voltage at an output thereof responsive to transition of the first pump signal line from a ground voltage to the power supply voltage. A second pump circuit includes a first switching circuit configured to couple a first capacitor between the output of the first pump circuit and a ground voltage node responsive to the transition of a first pump signal line from the ground voltage to the power supply voltage to charge the first capacitor to the first voltage, and to couple a second capacitor between the first capacitor and a second pump signal line responsive to a transition of the second pump signal line from the ground voltage to the power supply voltage to generate a second voltage greater than the first voltage.Type: ApplicationFiled: January 10, 2006Publication date: August 10, 2006Inventor: Kwun-Soo Cheon