Patents by Inventor Kye Hyun Baek
Kye Hyun Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240099007Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically oveType: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
-
Patent number: 11903196Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically oveType: GrantFiled: December 18, 2020Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
-
Publication number: 20230017241Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Inventors: S M Istiaque Hossain, Tom J. John, Darwin A. Clampitt, Anilkumar Chandolu, Prakash Rau Mokhna Rau, Christopher J. Larsen, Kye Hyun Baek
-
Patent number: 11482536Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.Type: GrantFiled: July 23, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: S M Istiaque Hossain, Tom J. John, Darwin A. Clampitt, Anilkumar Chandolu, Prakash Rau Mokhna Rau, Christopher J. Larsen, Kye Hyun Baek
-
Publication number: 20220223702Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Chang-yeon LEE, Jin-wook LEE, Min-chan GWAK, Kye-Hyun BAEK, Hong-bae PARK
-
Publication number: 20220199641Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically oveType: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
-
Patent number: 11309393Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.Type: GrantFiled: May 7, 2019Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-yeon Lee, Jin-wook Lee, Min-chan Gwak, Kye-Hyun Baek, Hong-bae Park
-
Publication number: 20220077285Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Jae-hyun PARK, Kye-hyun BAEK, Yong-ho JEON, Cheol KIM, Sung-il PARK, Yun-il LEE, Hyung-suk LEE
-
Publication number: 20220028881Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.Type: ApplicationFiled: July 23, 2020Publication date: January 27, 2022Inventors: S M Istiaque Hossain, Tom J. John, Darwin A. Clampitt, Anilkumar Chandolu, Prakash Rau Mokhna Rau, Christopher J. Larsen, Kye Hyun Baek
-
Patent number: 11211450Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: GrantFiled: July 12, 2018Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
-
Patent number: 10991825Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom. The plurality of fins includes a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins. The device also includes at least one gate electrode crossing at least a portion of the active fins. The device further includes a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin.Type: GrantFiled: October 23, 2018Date of Patent: April 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheol Kim, Jong Chui Park, Kye Hyun Baek
-
Publication number: 20200035796Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.Type: ApplicationFiled: May 7, 2019Publication date: January 30, 2020Inventors: Chang-yeon LEE, Jin-wook LEE, Min-chan GWAK, Kye-Hyun BAEK, Hong-bae PARK
-
Publication number: 20190288114Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom. The plurality of fins includes a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins. The device also includes at least one gate electrode crossing at least a portion of the active fins. The device further includes a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin.Type: ApplicationFiled: October 23, 2018Publication date: September 19, 2019Inventors: Cheol Kim, Jong Chul Park, Kye Hyun Baek
-
Publication number: 20190280087Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: ApplicationFiled: July 12, 2018Publication date: September 12, 2019Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
-
Patent number: 9912258Abstract: An electrostatic chuck assembly, including an electrostatic chuck on which a substrate is loaded; a channel that provides a flow passage for coolant in the electrostatic chuck, the channel having a first opening at a first end corresponding to a center of the substrate and a second opening at a second end corresponding to an edge of the substrate; and a valve box to control a flow direction of the coolant in the channel, the valve box including a first supply valve to control an introduction of the coolant into the first opening; a first return valve to control a drainage of the coolant from the second opening; a second supply valve to control an introduction of the coolant into the second opening; and a second return valve to control a drainage of the coolant from the first opening.Type: GrantFiled: September 2, 2015Date of Patent: March 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Haejoong Park, Hongmyoung Kim, Kye Hyun Baek, Sangkyu Park
-
Patent number: 9870900Abstract: Provided are methods and systems for managing semiconductor manufacturing equipment. A method may include preventive maintenance involving steps of disassembling, cleaning, and assembling parts of a chamber. The assembling of the parts may include checking whether the parts are correctly assembled, using reflectance and absorptivity of a high-frequency voltage applied to the parts.Type: GrantFiled: February 25, 2015Date of Patent: January 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kye Hyun Baek, Ohyung Kwon, Junghyun Cho, Haejoong Park
-
Patent number: 9859175Abstract: Provided are substrate processing systems and methods of managing the same. The method may include displaying a notification for a preventive maintenance operation on a chamber, performing a maintenance operation on the chamber, performing a first optical test, and evaluating the preventive maintenance operation. The first optical test may include generating a reference plasma reaction, measuring a variation of intensity by wavelength for plasma light emitted from the reference plasma reaction, and calculating an electron density and an electron temperature from a ratio in intensity of the plasma light.Type: GrantFiled: April 29, 2016Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiwook Song, Bum-Soo Kim, Kye Hyun Baek, Masayuki Tomoyasu, Eunwoo Lee, Jong Seo Hong
-
Publication number: 20170047200Abstract: A plasma processing apparatus includes a chamber defining a process space, an upper electrode mounted in the chamber, the upper electrode including a first gas spray port located in a central region of the upper electrode and a second gas spray port located in a peripheral region of the upper electrode, a lower electrode located opposite the upper electrode across the process space, a first gas supply unit configured to supply a first process gas into the process space via the first gas spray port and the second gas spray port, a second gas supply unit configured to supply a second process gas into the process space via the second gas spray port, a sensor configured to sense a state of plasma in an edge portion of the process space, and a controller configured to control the second gas supply unit in response to an output signal of the sensor.Type: ApplicationFiled: April 13, 2016Publication date: February 16, 2017Inventors: Hyung-Joo Lee, Kye-hyun Baek, Masayuki Tomoyasu, Jong-seo Hong, Jin-pyoung Kim
-
Publication number: 20170032987Abstract: Disclosed are a dry etching apparatus and a method of etching a substrate using the same. The apparatus includes a base at a lower portion of process chamber in which a dry etching process is performed, a substrate holder arranged on the base and holding a substrate on which a plurality of pattern structures is formed by the etching process, a focus ring enclosing the substrate holder and uniformly focusing an etching plasma to a sheath area over the substrate, a driver driving the focus ring in a vertical direction perpendicular to the base and a position controller controlling a vertical position of the focus ring by selectively driving the driver in accordance with inspection results of the pattern structures. Accordingly, the gap distance between the substrate and the focus ring is automatically controlled to thereby increase the uniformity of the etching plasma over the substrate.Type: ApplicationFiled: April 12, 2016Publication date: February 2, 2017Inventors: Hyung-Joo LEE, Kwang-Nam KIM, Jong-Seo HONG, Kye-Hyun BAEK, Masayuki TOMOYASU
-
Publication number: 20160372386Abstract: Provided are substrate processing systems and methods of managing the same. The method may include displaying a notification for a preventive maintenance operation on a chamber, performing a maintenance operation on the chamber, performing a first optical test, and evaluating the preventive maintenance operation. The first optical test may include generating a reference plasma reaction, measuring a variation of intensity by wavelength for plasma light emitted from the reference plasma reaction, and calculating an electron density and an electron temperature from a ratio in intensity of the plasma light.Type: ApplicationFiled: April 29, 2016Publication date: December 22, 2016Inventors: Kiwook SONG, Bum-Soo KIM, Kye Hyun BAEK, MASAYUKI TOMOYASU, Eunwoo LEE, JONG SEO HONG