Abstract: A pipe register includes: a plurality of register units configured to output data in response to control signals; and a pipe control circuit configured to generate a reference timing signal by dividing a clock signal, the clock signal activated during an activation time of a read enable signal, and generate the control signals based on the read enable signal and the reference timing signal.

Abstract: The present invention relates to novel mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, a novel crystalline form thereof, and a process for preparing the same. More specifically, the present invention relates to mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, which is excellent in stability, solubility, and bioavailability when it is administered not only alone but also in combination with other drugs and which has a high purity, a crystalline form thereof, and a process for preparing the same.

Abstract: One exemplary embodiment of the present invention relates to a thermal management fluid module for a vehicle using a circulating fluid such as a refrigerant or a coolant, the thermal management fluid module including a manifold plate in which a plurality of fluid flow channels are formed, and a thermal interference avoidance unit which is coupled to the manifold plate and in which fluid flow channels having a relatively high temperature or low temperature are formed to be separated and spaced apart from other fluid flow channels among the fluid flow channels.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: The inventive concept provides a substrate treating method. The substrate treating method includes supplying a dissolving solution onto a rotating substrate; and supplying, after the supplying a dissolution solution, a treating liquid including a polymer onto the rotating substrate to form a liquid film.

Abstract: A separator for a fuel cell includes a reaction region, a pair of manifold regions on opposite sides of the reaction region and through which a plurality of manifolds pass, configured to introduce or discharge reaction gas or coolant, and a pair of diffusion regions between the reaction region and the manifold regions, configured to diffuse a flow of the reaction gas or coolant. Diffusion ribs in the diffusion regions are spaced apart from each other along the manifolds. The diffusion ribs may be spaced apart such that diffusion flow fields formed between the diffusion ribs have different cross-sectional areas for respective regions at ends adjacent to the manifold regions.

Abstract: A current supply circuit according to the present disclosure may include a voltage/current converter configured to convert, into a data current, a data voltage received from a data driving circuit and a first current mirror circuit configured to mirror the data current so that a light-emitting diode (LED) current flows into an LED array. The data current may be adjusted based on a greyscale value of the LED array.

Abstract: A separator assembly for a fuel cell and a fuel cell stack including the same, is uniformly capable of forming a surface pressure of a region where a reaction gas flows when a stack is stacked by adjusting a height and shape of a gasket line for each region in which the reaction gas flows.

Abstract: A tray includes a main body portion including a bottom surface portion and a sidewall portion; and a plurality of first guide portions disposed on the bottom surface portion and arranged to be spaced apart from each other in a first direction. Each of the first guide portions includes a first main protruding portion, a first sub-protruding portion which protrudes from the first main protruding portion in the first direction, and a second sub-protruding portion which protrudes from the first main protruding portion in a direction opposite to the first direction, and the first sub-protruding portion and the second sub-protruding portion are alternately arranged in a direction the first main protruding portion extends.

Abstract: The present invention relates to a beam shaping device for a boron neutron capture therapy apparatus and the boron neutron capture therapy apparatus comprising same allowing a user to select the number of filter modules in advance before neutron generation and arrange same. According to the present invention, it is possible to improve a therapeutic effect and minimize side effects during boron neutron capture therapy.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: A cassette for receiving at least one substrate for a display device includes a base; and a first wall extending in a direction generally perpendicular to an upper surface of the base and a plurality of first projections extending from the first wall in a first direction and arranged in a second direction generally perpendicular to the first direction at substantially regular intervals. A first opening is defined between adjacent first projections to receive one end of a first substrate, the first opening includes a first portion having a first width in the second direction and a second portion having a second width greater than the first width, and the first portion is disposed closer to the first wall than the second portion.

Abstract: A semiconductor package may include: a substrate having a first side and a second side on a same plane; a first semiconductor chip disposed over the second side of the substrate; a first one-side third semiconductor chip stack disposed over the first side of the substrate and spaced apart from the first semiconductor chip; a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack, wherein each of the third semiconductor chip stacks includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, each of the third semiconductor chip stacks being electrically connected to the substrate.

Abstract: A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n?1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: A cassette for receiving at least one substrate for a display device includes a base; and a first wall extending in a direction generally perpendicular to an upper surface of the base and a plurality of first projections extending from the first wall in a first direction and arranged in a second direction generally perpendicular to the first direction at substantially regular intervals. A first opening is defined between adjacent first projections to receive one end of a first substrate, the first opening includes a first portion having a first width in the second direction and a second portion having a second width greater than the first width, and the first portion is disposed closer to the first wall than the second portion.

Abstract: A tray includes a main body portion including a bottom surface portion and a sidewall portion; and a plurality of first guide portions disposed on the bottom surface portion and arranged to be spaced apart from each other in a first direction. Each of the first guide portions includes a first main protruding portion, a first sub-protruding portion which protrudes from the first main protruding portion in the first direction, and a second sub-protruding portion which protrudes from the first main protruding portion in a direction opposite to the first direction, and the first sub-protruding portion and the second sub-protruding portion are alternately arranged in a direction the first main protruding portion extends.