Abstract: A semiconductor device includes a memory cell array, a first pre-charge circuit, and a data line switching control circuit. The memory cell array includes a first data line, a second data line, and a third data line. The first pre-charge circuit is configured to pre-charge the first data line according to a first voltage level of a first equalizing signal. The data line switching control circuit is configured to disconnect the second data line from the third data line according to a second voltage level of a data line switching control signal in a standby operation of the semiconductor device, to perform charge sharing of the first equalizing signal and the data line switching control signal for a first time in an active operation of the semiconductor device, and to drive the data line switching control signal to the first voltage level.

Abstract: A semiconductor device includes a memory cell array, a first pre-charge circuit, and a data line switching control circuit. The memory cell array includes a first data line, a second data line, and a third data line. The first pre-charge circuit is configured to pre-charge the first data line according to a first voltage level of a first equalizing signal. The data line switching control circuit is configured to disconnect the second data line from the third data line according to a second voltage level of a data line switching control signal in a standby operation of the semiconductor device, to perform charge sharing of the first equalizing signal and the data line switching control signal for a first time in an active operation of the semiconductor device, and to drive the data line switching control signal to the first voltage level.

Abstract: A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.

Abstract: An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.

Abstract: A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.

Abstract: A sense amplifier control circuit of a semiconductor apparatus includes a driving unit configured to apply a first voltage to a sense amplifier in response to a first driving signal. The driving unit may also be configured to apply a second voltage to the sense amplifier in response to a second driving signal. In addition, the driving unit may also be configured to apply a third voltage to the sense amplifier in response to a third driving signal. A switching unit may be configured to electrically couple a first node to a second node in response to a control signal. The first driving signal is output to the first node, and the second driving signal is output to the second node.

Abstract: A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple the first voltage line with the second voltage line and decouple the first voltage line from the second voltage line in response to a switching control signal.

Abstract: A sense amplifier control circuit of a semiconductor apparatus includes a driving unit configured to apply a first voltage to a sense amplifier in response to a first driving signal. The driving unit may also be configured to apply a second voltage to the sense amplifier in response to a second driving signal. In addition, the driving unit may also be configured to apply a third voltage to the sense amplifier in response to a third driving signal. A switching unit may be configured to electrically couple a first node to a second node in response to a control signal. The first driving signal is output to the first node, and the second driving signal is output to the second node.

Abstract: A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple the first voltage line with the second voltage line and decouple the first voltage line from the second voltage line in response to a switching control signal.

Abstract: A semiconductor memory device includes a fuse unit including a fuse configured to be programmed with a repair target address, an enable unit configured to enable the fuse unit, an output unit configured to output a signal corresponding to whether the fuse unit is programmed or not, and a control unit configured to control a voltage difference between both ends of the fuse unit in response to a control signal.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals.

Abstract: A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation.