Patents by Inventor Kyeong Rho Kim

Kyeong Rho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230068089
    Abstract: A memory system may include: a memory device; and a controller. When at least one data group is received, the data group including a plurality of data which is required to be collectively processed, the controller reads preceding logical-to-physical (L2P) map information for the data group from a first table and stores the read L2P map information in a second table before reception of the plurality of the data of the data group is committed, and the controller stores the plurality of the data in the memory device, and the controller updates the L2P map information for the data group that is stored in the first table in response to the storing of the plurality of the data in the memory device.
    Type: Application
    Filed: October 28, 2022
    Publication date: March 2, 2023
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Dong-Hyun CHO
  • Patent number: 11403177
    Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: August 2, 2022
    Assignee: SK hynix Inc.
    Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Sung-Kwan Hong
  • Patent number: 11372721
    Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Sung-Kwan Hong
  • Patent number: 11340790
    Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventors: Joo Young Lee, Kyeong Rho Kim, Kyung Hoon Lee
  • Publication number: 20210011843
    Abstract: A memory system may include: a memory device; and a controller. When at least one data group is received, the data group including a plurality of data which is required to be collectively processed, the controller reads preceding logical-to-physical (L2P) map information for the data group from a first table and stores the read L2P map information in a second table before reception of the plurality of the data of the data group is committed, and the controller stores the plurality of the data in the memory device, and the controller updates the L2P map information for the data group that is stored in the first table in response to the storing of the plurality of the data in the memory device.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Dong-Hyun CHO, Su-Chang KIM
  • Patent number: 10838874
    Abstract: A memory system includes a non-volatile memory device including a plurality of memory blocks; and a controller comprising a volatile memory and configured to: store a plurality of write data delivered from a host in the memory blocks to the plurality of memory blocks; and managing mapping information corresponding to the stored write data in the volatile memory, wherein the controller is configured to check whether the plurality of write data are grouped into a transaction, selectively set a transaction flag to the mapping information based on a check result; and selectively store the mapping information in the memory blocks when the transaction flag is not set.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Sung-Kwan Hong, Su-Chang Kim, Yeong-Sik Yi, Ji-Hoon Yim
  • Publication number: 20200341850
    Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Sung-Kwan HONG
  • Patent number: 10733056
    Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Sung-Kwan Hong
  • Patent number: 10725905
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages; and a controller suitable for, when writing a plurality of data in the pages according to a write request from a host, writing the plurality of data with tags, classified into N number of kinds depending on a usage pattern of each data, together in the pages. The controller manages a list of victim blocks as a target of a merge operation, the controller manages entire valid pages included in the victim blocks, by classifying them into N number of page groups depending on a kind of each of the entire valid pages, and the controller selects valid pages to be moved to a free block in the merge operation, among the entire valid pages, and N may be a natural number of 2 or greater.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Jin-Woong Kim, Hui-Won Lee, Eun-Soo Jang
  • Publication number: 20200050362
    Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Joo Young LEE, Kyeong Rho KIM, Kyung Hoon LEE
  • Patent number: 10558382
    Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for grouping the memory blocks based on type into a plurality of super blocks according to a preset condition and managing the memory blocks by managing the super blocks, the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks, and the controller may differently manage uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Ik-Sung Oh, Kyeong-Rho Kim, Sung-Kwan Hong, Jin-Woong Kim
  • Patent number: 10466905
    Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Joo Young Lee, Kyeong Rho Kim, Kyung Hoon Lee
  • Publication number: 20190310774
    Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for grouping the memory blocks based on type into a plurality of super blocks according to a preset condition and managing the memory blocks by managing the super blocks, the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks, and the controller may differently manage uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks.
    Type: Application
    Filed: November 9, 2018
    Publication date: October 10, 2019
    Inventors: Ik-Sung OH, Kyeong-Rho KIM, Sung-Kwan HONG, Jin-Woong KIM
  • Publication number: 20190278518
    Abstract: A memory system may include: a memory device including a plurality of pages in which data are stored and a plurality of memory blocks in which the pages are included; and a controller including a first memory, the controller may check operations to be performed in the memory blocks, may schedule queues corresponding to the operations, allocates the first memory and a second memory included in a host to memory regions corresponding to the scheduled queues, may perform the operations through the memory regions allocated in the first memory and the second memory, and may record information on the operations, the queues and the memory regions in a table.
    Type: Application
    Filed: October 31, 2018
    Publication date: September 12, 2019
    Inventors: Eu-Joon BYUN, Kyeong-Rho KIM
  • Publication number: 20190205246
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages; and a controller suitable for, when writing a plurality of data in the pages according to a write request from a host, writing the plurality of data with tags, classified into N number of kinds depending on a usage pattern of each data, together in the pages. The controller manages a list of victim blocks as a target of a merge operation, the controller manages entire valid pages included in the victim blocks, by classifying them into N number of page groups depending on a kind of each of the entire valid pages, and the controller selects valid pages to be moved to a free block in the merge operation, among the entire valid pages, and N may be a natural number of 2 or greater.
    Type: Application
    Filed: August 10, 2018
    Publication date: July 4, 2019
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Jin-Woong KIM, Hui-Won LEE, Eun-Soo JANG
  • Publication number: 20190138454
    Abstract: A memory system includes a non-volatile memory device including a plurality of memory blocks; and a controller comprising a volatile memory and configured to: store a plurality of write data delivered from a host in the memory blocks to the plurality of memory blocks; and managing mapping information corresponding to the stored write data in the volatile memory, wherein the controller is configured to check whether the plurality of write data are grouped into a transaction, selectively set a transaction flag to the mapping information based on a check result; and selectively store the mapping information in the memory blocks when the transaction flag is not set.
    Type: Application
    Filed: June 7, 2018
    Publication date: May 9, 2019
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Sung-Kwan HONG, Su-Chang KIM, Yeong-Sik YI, Ji-Hoon YIM
  • Publication number: 20190121701
    Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.
    Type: Application
    Filed: June 5, 2018
    Publication date: April 25, 2019
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Sung-Kwan HONG
  • Publication number: 20190012081
    Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.
    Type: Application
    Filed: December 6, 2017
    Publication date: January 10, 2019
    Inventors: Joo Young LEE, Kyeong Rho Kim, Kyung Hoon Lee
  • Patent number: 10157024
    Abstract: A memory system may include: a memory device including a plurality of memory blocks which include pages; and a controller suitable for: performing command operations in response to commands, recording a count information of the respective memory blocks in a count information table according to the command operations, listing memory blocks satisfying a predetermined first condition in a source memory block candidate list by referring to the count information corresponding to a offset, and selecting as a source memory block a memory block satisfying a predetermined second condition among the memory blocks listed in the source memory block candidate list. The offset may indicate a difference between the count information of the respective memory blocks and an average of the count information.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 18, 2018
    Assignee: SK Hynix Inc.
    Inventors: Se-Hyun Kim, Kyeong-Rho Kim
  • Publication number: 20180341576
    Abstract: A memory system may include: a memory device; and a controller. When at least one data group is received, the data group including a plurality of data which is required to be collectively processed, the controller reads preceding logical-to-physical (L2P) map information for the data group from a first table and stores the read L2P map information in a second table before reception of the plurality of the data of the data group is committed, and the controller stores the plurality of the data in the memory device, and the controller updates the L2P map information for the data group that is stored in the first table in response to the storing of the plurality of the data in the memory device.
    Type: Application
    Filed: November 20, 2017
    Publication date: November 29, 2018
    Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Dong-Hyun CHO, Su-Chang KIM