Patents by Inventor Kyeong Rho Kim
Kyeong Rho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230068089Abstract: A memory system may include: a memory device; and a controller. When at least one data group is received, the data group including a plurality of data which is required to be collectively processed, the controller reads preceding logical-to-physical (L2P) map information for the data group from a first table and stores the read L2P map information in a second table before reception of the plurality of the data of the data group is committed, and the controller stores the plurality of the data in the memory device, and the controller updates the L2P map information for the data group that is stored in the first table in response to the storing of the plurality of the data in the memory device.Type: ApplicationFiled: October 28, 2022Publication date: March 2, 2023Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Dong-Hyun CHO
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Patent number: 11403177Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.Type: GrantFiled: July 10, 2020Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Sung-Kwan Hong
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Patent number: 11372721Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.Type: GrantFiled: July 10, 2020Date of Patent: June 28, 2022Assignee: SK hynix Inc.Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Sung-Kwan Hong
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Patent number: 11340790Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.Type: GrantFiled: October 17, 2019Date of Patent: May 24, 2022Assignee: SK hynix Inc.Inventors: Joo Young Lee, Kyeong Rho Kim, Kyung Hoon Lee
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Publication number: 20210011843Abstract: A memory system may include: a memory device; and a controller. When at least one data group is received, the data group including a plurality of data which is required to be collectively processed, the controller reads preceding logical-to-physical (L2P) map information for the data group from a first table and stores the read L2P map information in a second table before reception of the plurality of the data of the data group is committed, and the controller stores the plurality of the data in the memory device, and the controller updates the L2P map information for the data group that is stored in the first table in response to the storing of the plurality of the data in the memory device.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Dong-Hyun CHO, Su-Chang KIM
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Patent number: 10838874Abstract: A memory system includes a non-volatile memory device including a plurality of memory blocks; and a controller comprising a volatile memory and configured to: store a plurality of write data delivered from a host in the memory blocks to the plurality of memory blocks; and managing mapping information corresponding to the stored write data in the volatile memory, wherein the controller is configured to check whether the plurality of write data are grouped into a transaction, selectively set a transaction flag to the mapping information based on a check result; and selectively store the mapping information in the memory blocks when the transaction flag is not set.Type: GrantFiled: June 7, 2018Date of Patent: November 17, 2020Assignee: SK hynix Inc.Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Sung-Kwan Hong, Su-Chang Kim, Yeong-Sik Yi, Ji-Hoon Yim
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Publication number: 20200341850Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Sung-Kwan HONG
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Patent number: 10733056Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.Type: GrantFiled: June 5, 2018Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Sung-Kwan Hong
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Patent number: 10725905Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages; and a controller suitable for, when writing a plurality of data in the pages according to a write request from a host, writing the plurality of data with tags, classified into N number of kinds depending on a usage pattern of each data, together in the pages. The controller manages a list of victim blocks as a target of a merge operation, the controller manages entire valid pages included in the victim blocks, by classifying them into N number of page groups depending on a kind of each of the entire valid pages, and the controller selects valid pages to be moved to a free block in the merge operation, among the entire valid pages, and N may be a natural number of 2 or greater.Type: GrantFiled: August 10, 2018Date of Patent: July 28, 2020Assignee: SK hynix Inc.Inventors: Hae-Gi Choi, Kyeong-Rho Kim, Su-Chang Kim, Jin-Woong Kim, Hui-Won Lee, Eun-Soo Jang
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Publication number: 20200050362Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Inventors: Joo Young LEE, Kyeong Rho KIM, Kyung Hoon LEE
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Patent number: 10558382Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for grouping the memory blocks based on type into a plurality of super blocks according to a preset condition and managing the memory blocks by managing the super blocks, the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks, and the controller may differently manage uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks.Type: GrantFiled: November 9, 2018Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Ik-Sung Oh, Kyeong-Rho Kim, Sung-Kwan Hong, Jin-Woong Kim
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Patent number: 10466905Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.Type: GrantFiled: December 6, 2017Date of Patent: November 5, 2019Assignee: SK hynix Inc.Inventors: Joo Young Lee, Kyeong Rho Kim, Kyung Hoon Lee
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Publication number: 20190310774Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for grouping the memory blocks based on type into a plurality of super blocks according to a preset condition and managing the memory blocks by managing the super blocks, the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks, and the controller may differently manage uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks.Type: ApplicationFiled: November 9, 2018Publication date: October 10, 2019Inventors: Ik-Sung OH, Kyeong-Rho KIM, Sung-Kwan HONG, Jin-Woong KIM
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Publication number: 20190278518Abstract: A memory system may include: a memory device including a plurality of pages in which data are stored and a plurality of memory blocks in which the pages are included; and a controller including a first memory, the controller may check operations to be performed in the memory blocks, may schedule queues corresponding to the operations, allocates the first memory and a second memory included in a host to memory regions corresponding to the scheduled queues, may perform the operations through the memory regions allocated in the first memory and the second memory, and may record information on the operations, the queues and the memory regions in a table.Type: ApplicationFiled: October 31, 2018Publication date: September 12, 2019Inventors: Eu-Joon BYUN, Kyeong-Rho KIM
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Publication number: 20190205246Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages; and a controller suitable for, when writing a plurality of data in the pages according to a write request from a host, writing the plurality of data with tags, classified into N number of kinds depending on a usage pattern of each data, together in the pages. The controller manages a list of victim blocks as a target of a merge operation, the controller manages entire valid pages included in the victim blocks, by classifying them into N number of page groups depending on a kind of each of the entire valid pages, and the controller selects valid pages to be moved to a free block in the merge operation, among the entire valid pages, and N may be a natural number of 2 or greater.Type: ApplicationFiled: August 10, 2018Publication date: July 4, 2019Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Jin-Woong KIM, Hui-Won LEE, Eun-Soo JANG
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Publication number: 20190138454Abstract: A memory system includes a non-volatile memory device including a plurality of memory blocks; and a controller comprising a volatile memory and configured to: store a plurality of write data delivered from a host in the memory blocks to the plurality of memory blocks; and managing mapping information corresponding to the stored write data in the volatile memory, wherein the controller is configured to check whether the plurality of write data are grouped into a transaction, selectively set a transaction flag to the mapping information based on a check result; and selectively store the mapping information in the memory blocks when the transaction flag is not set.Type: ApplicationFiled: June 7, 2018Publication date: May 9, 2019Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Sung-Kwan HONG, Su-Chang KIM, Yeong-Sik YI, Ji-Hoon YIM
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Publication number: 20190121701Abstract: A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.Type: ApplicationFiled: June 5, 2018Publication date: April 25, 2019Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Su-Chang KIM, Sung-Kwan HONG
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Publication number: 20190012081Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.Type: ApplicationFiled: December 6, 2017Publication date: January 10, 2019Inventors: Joo Young LEE, Kyeong Rho Kim, Kyung Hoon Lee
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Patent number: 10157024Abstract: A memory system may include: a memory device including a plurality of memory blocks which include pages; and a controller suitable for: performing command operations in response to commands, recording a count information of the respective memory blocks in a count information table according to the command operations, listing memory blocks satisfying a predetermined first condition in a source memory block candidate list by referring to the count information corresponding to a offset, and selecting as a source memory block a memory block satisfying a predetermined second condition among the memory blocks listed in the source memory block candidate list. The offset may indicate a difference between the count information of the respective memory blocks and an average of the count information.Type: GrantFiled: September 12, 2017Date of Patent: December 18, 2018Assignee: SK Hynix Inc.Inventors: Se-Hyun Kim, Kyeong-Rho Kim
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Publication number: 20180341576Abstract: A memory system may include: a memory device; and a controller. When at least one data group is received, the data group including a plurality of data which is required to be collectively processed, the controller reads preceding logical-to-physical (L2P) map information for the data group from a first table and stores the read L2P map information in a second table before reception of the plurality of the data of the data group is committed, and the controller stores the plurality of the data in the memory device, and the controller updates the L2P map information for the data group that is stored in the first table in response to the storing of the plurality of the data in the memory device.Type: ApplicationFiled: November 20, 2017Publication date: November 29, 2018Inventors: Hae-Gi CHOI, Kyeong-Rho KIM, Dong-Hyun CHO, Su-Chang KIM