Patents by Inventor Kyeongbeom Park
Kyeongbeom Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085812Abstract: A substrate processing apparatus includes a chamber having an internal space configured to process a substrate loaded therein; a light source configured to emit light on the substrate to harden a photoresist pattern coated on the substrate; and a transparent division part provided between the substrate and the light source, wherein the transparent division part divides the chamber into a first space, in which the light source is provided, and a second space, in which the substrate is provided.Type: ApplicationFiled: August 4, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyuhee Han, Koungmin Ryu, Kyeongbeom Park, Jongmin Baek, Wookyung You, Woojin Lee, Juhee Lee
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Publication number: 20240030127Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: ApplicationFiled: August 9, 2023Publication date: January 25, 2024Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11764149Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: GrantFiled: July 18, 2022Date of Patent: September 19, 2023Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11646263Abstract: A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.Type: GrantFiled: January 22, 2021Date of Patent: May 9, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wookyung You, Kyeongbeom Park, Sungbin Park, Suhyun Park, Jongmin Baek, Jangho Lee, Seonghun Lim, Deokyoung Jung, Kyuhee Han
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Publication number: 20230042905Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.Type: ApplicationFiled: March 25, 2022Publication date: February 9, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Yongchul JEONG, Sangjin KIM, Yigwon KIM, Kyeongbeom PARK, Suhyun BARK, Sangshin JANG, Jinhee JANG, Cheolin JANG, Tae Min CHOI
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Publication number: 20230027640Abstract: A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.Type: ApplicationFiled: March 21, 2022Publication date: January 26, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jongmin BAEK, Junghoo SHIN, Sangshin JANG, Junghwan CHUN, Kyeongbeom PARK, Suhyun BARK
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Publication number: 20220359379Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: ApplicationFiled: July 18, 2022Publication date: November 10, 2022Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Patent number: 11424182Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: GrantFiled: December 22, 2020Date of Patent: August 23, 2022Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
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Publication number: 20210391254Abstract: A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.Type: ApplicationFiled: January 22, 2021Publication date: December 16, 2021Inventors: Wookyung You, Kyeongbeom Park, Sungbin Park, Suhyun Park, Jongmin Baek, Jangho Lee, Seonghun Lim, Deokyoung Jung, Kyuhee Han
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Publication number: 20210351123Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.Type: ApplicationFiled: December 22, 2020Publication date: November 11, 2021Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung