Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Abstract: ESD protection apparatus disclosed herein include an ESD trigger circuit to sense the occurrence of an ESD event and an ESD discharge device to provide a low impedance path to ground through which to discharge energy associated with the ESD pulse. Some embodiments also include a VDD turn-on clamp to prevent the ESD discharge device from switching to a conductive state during a VDD power-on event. Some embodiments further include a VDD glitch clamp to prevent a switching pulse triggered by a transient disruption in the VDD supply from propagating to the ESD discharge device and causing the ESD discharge device to conduct in the absence of an ESD event.

Abstract: ESD protection apparatus disclosed herein include an ESD trigger circuit to sense the occurrence of an ESD event and an ESD discharge device to provide a low impedance path to ground through which to discharge energy associated with the ESD pulse. Some embodiments also include a VDD turn-on clamp to prevent the ESD discharge device from switching to a conductive state during a VDD power-on event. Some embodiments further include a VDD glitch clamp to prevent a switching pulse triggered by a transient disruption in the VDD supply from propagating to the ESD discharge device and causing the ESD discharge device to conduct in the absence of an ESD event.