Abstract: Disclosed is a semiconductor memory device comprising a pipeline structure having a sense amplifier responsive to a first enable signal; a data register responsive to a second enable signal for latching an output of said sense amplifier between said sense amplifier and a common data line; and a monitoring part to monitor said first and second enable signals and adapted to prevent overlapping between an enabling interval of said first enable signal and said second enable signal.

Abstract: A synchronous semiconductor memory device includes a plurality of main data lines each coupled between a block sense amplifier array and a data output buffer. Each main data line prefetches a plurality of cell data segments from memory cells corresponding to an input/output port and transmits the cell data to the data output buffer. The memory device also includes a pass/latch part connected to one or more corresponding block sense amplifiers within a corresponding block sense amplifier array. The pass/latch part receives a plurality of cell data segments in parallel from the block sense amplifiers and transmits them in series to a corresponding main data line. This invention reduces a chip size and peak electric current of the semiconductor device by minimizing the number of main data lines required for prefetch operations.

Abstract: An internal power voltage generating circuit for a semiconductor device reduces current consumption during stand-by mode and allows a fast transition to active mode by using a single output driver for both standby mode and active mode. The output driver is coupled to both an active mode comparison circuit, which is disabled during stand-by-mode, and a stand-by mode comparison circuit which is enabled during stand-by-mode. The active mode comparison circuit is fabricated from large transistors and generates a first output signal having a high current capacity to turn the output driver completely on. The stand-by mode comparison circuit is fabricated from small transistors and generators a second output signal having a low current capacity which only turns the output driver partially on. The output driver can switch quickly from stand-by-mode to active mode because it is not turned completely off during stand-by-mode. This also eliminates the need for an additional circuit for turning the driver completely off.

Abstract: The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.

Abstract: The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.