Abstract: An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to the internal circuit of the LSI chip. Each sub-buffer circuit area has a plurality of basic elements, such as transistors and resistors, connected in parallel to one another so that different combinations of those elements can be selected by switches. A latch controller is incorporated in the LSI chip, and it has latch circuits serially connected to form a shift register structure. This latch controller sends a program signal for determining the buffer circuit characteristic to the sub-buffer circuit areas. This program signal is generated when program data is input to the latch controller. The program data is given serially via input buffers from the pads on the LSI chip. The latch controller transfers the program data to the latch circuits one after another in synchronism with a clock signal.

Abstract: For increasing the number of pads to be connected to external terminals such as leads of a lead frame without increasing an area of a semiconductor IC chip, pads are disposed at a periphery of the chip in such a manner that they are arranged in at least first and second rows, to which at least first and second groups of interconnection layers insulated through an interval insulator are electrically connected, respectively.