Patents by Inventor Kyoichi Yahata

Kyoichi Yahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7800673
    Abstract: A solid-state imaging device and an optical sensor, which can enhance a wide dynamic range while keeping a high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping a high sensitivity with a high S/N ratio are disclosed. An array of integrated pixels has a structure wherein each pixel comprises a photodiode PD for receiving light and generating and accumulating photoelectric charges and a storage capacitor element CS coupled to the photodiode PD through a transfer transistor Tr1 for accumulating the photoelectric charges overflowing from the photodiode PD. The storage capacitor element CS is structured to accumulate the photoelectric charges overflowing from the photodiode PD in a storage-capacitor-element accumulation period TCS that is set to be a period at a predetermined ratio with respect to an accumulation period of the photodiode PD.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: September 21, 2010
    Assignee: National University Corporation Tohoku University
    Inventors: Shigetoshi Sugawa, Satoru Adachi, Kyoichi Yahata, Tatsuya Terada
  • Publication number: 20080266434
    Abstract: A solid-state imaging device and an optical sensor, which can enhance a wide dynamic range while keeping a high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping a high sensitivity with a high S/N ratio are disclosed. An array of integrated pixels has a structure wherein each pixel comprises a photodiode PD for receiving light and generating and accumulating photoelectric charges and a storage capacitor element CS coupled to the photodiode PD through a transfer transistor Tr1 for accumulating the photoelectric charges overflowing from the photodiode PD. The storage capacitor element CS is structured to accumulate the photoelectric charges overflowing from the photodiode PD in a storage-capacitor-element accumulation period TCS that is set to be a period at a predetermined ratio with respect to an accumulation period of the photodiode PD.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 30, 2008
    Inventors: Shigetoshi Sugawa, Satoru Adachi, Kyoichi Yahata, Tatsuya Terada
  • Patent number: 6862333
    Abstract: This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such as M sections (U1-UM), each of which is a CMD unit U that can perform a charge multiplication operation, set in series. Each section of CMD unit Ui has plural (such as 4) electrodes G1, G2, G3, G4 set in a row via an insulating film, such as silicon oxide film 100, on a silicon insulating film. Among driving voltages P1, P2, P3, P4 applied on the electrodes G1, G2, G3 and G4, P1 and P2 are applied in the same cycle as the transfer clock, P4 for impact ionization is applied in intermittent cycles with respect to P1 and P2, and P3 is applied as a DC voltage at a prescribed level.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Shunji Kashima, Kyoichi Yahata, Izumi Kobayashi
  • Publication number: 20030223531
    Abstract: This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such as M sections (U1-UM), each of which is a CMD unit U that can perform a charge multiplication operation, set in series. Each section of CMD unit Ui has plural (such as 4) electrodes G1, G2, G3, G4 set in a row via an insulating film, such as silicon oxide film 100, on a silicon insulating film. Among driving voltages P1, P2, P3, P4 applied on the electrodes G1, G2, G3 and G4, P1 and P2 are applied in the same cycle as the transfer clock, P4 for impact ionization is applied in intermittent cycles with respect to P1 and P2, and P3 is applied as a DC voltage at a prescribed level.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 4, 2003
    Inventors: Shunji Kashima, Kyoichi Yahata, Izumi Kobayashi