Patents by Inventor Kyoji Shibutani

Kyoji Shibutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11153068
    Abstract: There is provided an encryption device to suppress calculation in the reverse direction in whitebox model encryption. The encryption device includes: having a predetermined relationship that outputs a plurality of output values according to a plurality of input values configured of plain text, with a part of the plurality of output values being inputted to a trapdoor one-way function, the predetermined relationship being defined by the output values that are not inputted to the trapdoor one-way function and one arbitrary input value of the plurality of input values; and having a property of encrypting a part of the plurality of output values according to the trapdoor one-way function, and the trapdoor one-way function not being able to decrypt encrypted data in a state in which a trapdoor is unknown.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 19, 2021
    Assignee: SONY CORPORATION
    Inventors: Takanori Isobe, Harunaga Hiwatari, Kyoji Shibutani
  • Patent number: 10425226
    Abstract: An encryption processing device includes an encryption processing section that repeats a round operation on input data and generate output data, and a key scheduling section that outputs a round key to be applied in the round operation to the encryption processing section. The encryption processing section has an involution property in which a data conversion function E and an inverse function E?1 are executed sequentially, and executes the round operation in which a constant is applied once or more in only one of the function E and the inverse function E?1. The constant is a state that satisfies a condition that all of constituent elements of a state which is a result of a matrix operation with the linear conversion matrix which is applied in the linear conversion processing section at a position adjacent to the exclusive-OR section to which the constant is input are nonzero.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: September 24, 2019
    Assignee: SONY CORPORATION
    Inventors: Kyoji Shibutani, Takanori Isobe
  • Patent number: 10341090
    Abstract: A cipher processing configuration, of which the resistance against various attacks is improved, having a high security level is realized. In a cipher processing configuration in which a nonlinear transformation process and a linear transformation process are repeatedly performed for state data formed from a plurality of elements, a linear transformation unit performs a matrix operation applying a quasi-MDS matrix and a substitution process. As the substitution process, a substitution process is performed which satisfies the following (Condition 1) and (Condition A).
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Kyoji Shibutani, Takanori Isobe
  • Publication number: 20190103957
    Abstract: There is provided an encryption device to suppress calculation in the reverse direction in whitebox model encryption. The encryption device includes: having a predetermined relationship that outputs a plurality of output values according to a plurality of input values configured of plain text, with a part of the plurality of output values being inputted to a trapdoor one-way function, the predetermined relationship being defined by the output values that are not inputted to the trapdoor one-way function and one arbitrary input value of the plurality of input values; and having a property of encrypting a part of the plurality of output values according to the trapdoor one-way function, and the trapdoor one-way function not being able to decrypt encrypted data in a state in which a trapdoor is unknown.
    Type: Application
    Filed: May 11, 2017
    Publication date: April 4, 2019
    Applicant: SONY CORPORATION
    Inventors: Takanori ISOBE, Harunaga HIWATARI, Kyoji SHIBUTANI
  • Patent number: 10205589
    Abstract: An encryption processing system includes an encryption processing circuit that executes a round calculation on input data and generates output data, and a key schedule circuit that outputs key data used in the encryption processing circuit to the encryption processing circuit. Each round calculation executed by the encryption processing circuit includes a linear conversion process executed by a linear conversion circuit, and the linear conversion circuit changes a linear conversion mode of the linear conversion process according to a round transition.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: February 12, 2019
    Assignee: SONY CORPORATION
    Inventors: Kyoji Shibutani, Takanori Isobe
  • Publication number: 20170295010
    Abstract: A cipher processing configuration, of which the resistance against various attacks is improved, having a high security level is realized. In a cipher processing configuration in which a nonlinear transformation process and a linear transformation process are repeatedlyperformed for state data formed from a plurality of elements, a linear transformation unit performs a matrix operation applying a quasi-MDS matrix and a substitution process. As the substitution process, a substitution process is performed which satisfies the following (Condition 1) and (Condition A).
    Type: Application
    Filed: August 20, 2015
    Publication date: October 12, 2017
    Inventors: KYOJI SHIBUTANI, TAKANORI ISOBE
  • Publication number: 20170118011
    Abstract: An encryption processing system includes an encryption processing circuit that executes a round calculation on input data and generates output data, and a key schedule circuit that outputs key data used in the encryption processing circuit to the encryption processing circuit. Each round calculation executed by the encryption processing circuit includes a linear conversion process executed by a linear conversion circuit, and the linear conversion circuit changes a linear conversion mode of the linear conversion process according to a round transition.
    Type: Application
    Filed: February 23, 2015
    Publication date: April 27, 2017
    Inventors: Kyoji SHIBUTANI, Takanori ISOBE
  • Publication number: 20170118016
    Abstract: An encryption process excellent in security and highly resistant to various attacks is realized. An encryption processing device includes an encryption processing section configured to repeat a round operation on input data and generate output data, and a key scheduling section configured to output a round key to be applied in the round operation by the encryption processing section to the encryption processing section. The encryption processing section has an involution property in which a data conversion function E and an inverse function E?1 of the data conversion function E are executed sequentially, and executes the round operation in which a constant is applied once or more in only one of the function E and the inverse function E?1.
    Type: Application
    Filed: February 24, 2015
    Publication date: April 27, 2017
    Applicant: SONY CORPORATION
    Inventors: KYOJI SHIBUTANI, TAKANORI ISOBE
  • Patent number: 9418245
    Abstract: Included is an encryption processing unit configured to divide and input configuration bits of data to be data processed into a plurality of lines, and to repeatedly execute data conversion processing of data for each line. The encryption processing unit includes an F function execution unit to input data from one line configuring the plurality of lines and generate converted data, an XOR calculation unit to execute an XOR calculation with other lines of data corresponding to the output from the F function, an intermediate data storage register to store intermediate data during the process of generating converted data in the F function execution unit, and an inverse calculation executing unit to calculate input data regarding the F function execution unit on the basis of the data stored in the intermediate storage register.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: August 16, 2016
    Assignee: SONY CORPORATION
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Patent number: 9363074
    Abstract: A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: June 7, 2016
    Assignee: SONY CORPORATION
    Inventors: Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Patent number: 9270458
    Abstract: An encryption processing device including an encryption processing part configured to divide configuration bits of data to be data processed into plural lines, and to input, and to repeatedly execute data conversion processing applying a round function to each line of data as a round calculation; and a key scheduling part configured to output round keys to a round calculation executing unit in the encryption processing part. The key scheduling part is a replacement type key scheduling part configured to generate plural round keys or round key configuration data by dividing a secret key stored beforehand into plural parts. The plural round keys are output to a round calculation executing unit sequentially executing in the encryption processing part such that a constant sequence is not repeated. The encryption processing configuration has a high level of security and a high level of resistance to repeated key attacks or other attacks.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: February 23, 2016
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Atsushi Mitsuda, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari
  • Patent number: 9083507
    Abstract: A miniaturized non-linear conversion unit is achieved. Included is an encryption processing part configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing applying a round function as to the data in each line, wherein the encryption processing part includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data, wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing, and wherein the non-linear conversion processing unit includes a repeating structure of a non-linear calculation unit made up from either one NAND or NOR, and either one XOR or XNOR calculation unit, and a bit replacement unit. The miniaturized non-linear conversion unit is achieved by this repeating configuration.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: July 14, 2015
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Patent number: 9083506
    Abstract: There is provided a highly secure cryptographic processing apparatus and method where an analysis difficulty is increased. In a Feistel type common key block encrypting process in which an SPN type F function having a nonlinear conversion section and a linear conversion section is repeatedly executed a plurality of rounds. The linear conversion process of an F function corresponding to each of the plurality of rounds is performed as a linear conversion process which employs an MDS (Maximum Distance Separable) matrix, and a linear conversion process is carried out which employs a different MDS matrix at least at each of consecutive odd number rounds and consecutive even number rounds. This structure makes it possible to increase the minimum number (a robustness index against a differential attack in common key block encryption) of the active S box in the entire encrypting function.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 14, 2015
    Assignee: SONY CORPORATION
    Inventors: Taizo Shirai, Kyoji Shibutani
  • Patent number: 8983062
    Abstract: A cryptographic processing unit divides and inputs constituent bits of data to be subjected to data processing to lines, and repeatedly performs a data converting operation using round functions on the data of the respective lines. The cryptographic processing unit inputs n/d-bit data obtained by dividing n-bit data as input data by a division number d to each line, and repeatedly performs a round calculation including a data converting operation using round functions. The n/d-bit data in each line having output data of the round calculations is divided into d/2 sets of data, and the divided data are combined to restructure d sets of n/d-bit data that are different from the output data of the round calculations of the previous stage. The restructured data is set as input data for round calculations of the next stage. The cryptographic processing realizes improved diffusion properties and a high level of security.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Patent number: 8843457
    Abstract: There is realized a data conversion device that performs generation of a hash value with improved analysis resistance and a high degree of safety. There are provided a stirring processing section performing a data stirring process on input data; and a compression processing section performing a data compression process on input data including data segments which are divisions of message data, the message data being a target of a data conversion. Part of multi-stage compression subsections is configured to perform a data compression process based on both of output of the stirring processing section and the data segments in the message data. There is provided such a configuration that the stirring process is executed at least on fixed timing of a compression processing round of plural rounds and thus, there is realized a data conversion device that performs generation of a hash value with improved analysis resistance and a high degree of safety.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Shiho Moriai, Toru Akishita, Tetsu Iwata
  • Patent number: 8824671
    Abstract: A data conversion algorithm achieving efficient data diffusion is achieved. For example, in a configuration where a various processes are executed on two data segments which are resultants of dividing a rectangular matrix of data containing arranged one-byte data blocks into two parts to perform data conversion, efficient data scrambling with less operation cost is achieved by executing a linear conversion process on one of the data segments, an exclusive OR operation between the two data segments, a shift process on one of the data segments, and a swap process between the two data segments. Moreover, cryptographic processing with a high security level is achieved by including nonlinear conversion or key application operation on the data segments.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Shiho Moriai, Toru Akishita, Tetsu Iwata
  • Publication number: 20140233729
    Abstract: There is provided a highly secure cryptographic processing apparatus and method where an analysis difficulty is increased. In a Feistel type common key block encrypting process in which an SPN type F function having a nonlinear conversion section and a linear conversion section is repeatedly executed a plurality of rounds. The linear conversion process of an F function corresponding to each of the plurality of rounds is performed as a linear conversion process which employs an MDS (Maximum Distance Separable) matrix, and a linear conversion process is carried out which employs a different MDS matrix at least at each of consecutive odd number rounds and consecutive even number rounds. This structure makes it possible to increase the minimum number (a robustness index against a differential attack in common key block encryption) of the active S box in the entire encrypting function.
    Type: Application
    Filed: December 30, 2013
    Publication date: August 21, 2014
    Inventors: Taizo SHIRAI, Kyoji SHIBUTANI
  • Patent number: 8787563
    Abstract: A data converter for generating a hash value for message data is disclosed. The data converter executes a data conversion process, which includes compression-function execution sections and process sequences in which divided data blocks constituting message data are processed in parallel. Each compression-function execution section performs a process, using a message scheduling section and a chaining variable processing section. The message scheduling section receives a corresponding divided data block of the message data and performs a message scheduling process. The chaining variable processing section receives an output from the message scheduling section and an intermediate value output from a preceding processing section, and generates output data, which has the same number of bits as in the intermediate value. The compression-function execution sections may use one or more message scheduling sections and chaining variable processing sections.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Shiho Moriai, Toru Akishita, Tetsu Iwata
  • Patent number: 8787568
    Abstract: A non-linear transformation processing structure having a high implementation efficiency and a high security is realized. Data transformation is performed using a first non-linear transformation part performing non-linear transformation using a plurality of small S-boxes; a linear transformation part receiving all the outputs from the first non-linear transformation part and performing data transformation using a matrix for performing optimal diffusion mappings; and a second non-linear transformation part including a plurality of small non-linear transformation parts that perform non-linear transformation on individual data units into which output data from the linear transformation part is divided. With this structure, appropriate data diffusion can be achieved without excessively increasing a critical path, and a structure with a high implementation efficiency and a high security can be achieved.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Taizo Shirai, Toru Akishita, Shiho Moriai
  • Publication number: 20140192973
    Abstract: A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus.
    Type: Application
    Filed: October 9, 2013
    Publication date: July 10, 2014
    Applicant: SONY CORPORATION
    Inventors: Taizo SHIRAI, Kyoji SHIBUTANI, Toru AKISHITA, Shiho MORIAI